Multistage set procedure for phase change memory
Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
1. A memory device, comprising:
a memory array including multiple memory cells of material that changes resistive state based on being in a crystalline state or a non-crystalline state, the memory cells having a thickness to cause a memory cell to be fully amorphized in all active areas of the memory cell in a non-crystalline state, and to lack sufficient crystal nuclei to promote crystal growth; and
interface circuitry coupled to the memory array to control access to the memory cells, including control to change a memory cell from the non-crystalline state to the crystalline state, including application of a nucleation temperature for a first period of time to create crystal nuclei, application of a crystal growth temperature higher than the nucleation temperature for a second period of time to promote crystal growth, and application of a termination temperature lower than the crystal growth temperature for a third period of time to set the crystalline state.
2. The memory device of claim 1 , wherein the interface circuitry is to control application of the nucleation temperature, the crystal growth temperature, and the termination temperature through control of an amount of current passing through the memory cell.
3. The memory device of claim 2 , wherein the interface circuitry includes a memory cell driver to control the amount of current passing through the memory cell.
4. The memory device of claim 1 , wherein the interface circuitry is further to cause application of an initial temperature prior to the application of the nucleation temperature, the initial temperature higher than the nucleation temperature and higher than the crystal growth temperature.
5. The memory device of claim 4 , wherein the interface circuitry is to cause application of the initial temperature for a period of time much shorter than the first period of time or the second period of time.
6. The memory device of claim 1 , wherein the interface circuitry is to cause application of the nucleation temperature as multiple separate sub-temperatures for multiple separate sub-periods of time.
7. The memory device of claim 1 , wherein the second period of time for crystal growth is at least twice as the first period of time for nucleation growth.
8. The memory device of claim 1 , wherein the memory cell comprises a phase change memory (PCM) cell.
9. A memory controller, comprising:
read/write hardware to interface with a memory cell of a memory device having a memory array including multiple memory cells of material that changes resistive state based on being in a crystalline state or a non-crystalline state, the memory cells having a thickness to cause a memory cell to be fully amorphized in all active areas of the memory cell in the non-crystalline state, and to lack sufficient crystal nuclei to promote crystal growth; and
a scheduler to schedule a write command to the memory cell to change the memory cell from the non-crystalline state to the crystalline state, including control of timing to enable the change of the memory cell including application of a nucleation temperature for a first period of time to create crystal nuclei, application of a crystal growth temperature higher than the nucleation temperature for a second period of time to promote crystal growth, and application of a termination temperature lower than the crystal growth temperature for a third period of time to set the crystalline state.
10. The memory controller of claim 9 , wherein the application of the nucleation temperature, the crystal growth temperature, and the termination temperature comprises application of different amounts of current passing through the memory cell.
11. The memory controller of claim 9 , wherein the scheduler is to schedule the write command including control of timing to enable application of an initial temperature prior to the application of the nucleation temperature, the initial temperature higher than the nucleation temperature and higher than the crystal growth temperature.
12. The memory controller of claim 11 , wherein application of the initial temperature comprises application for a period of time much shorter than the first period of time or the second period of time.
13. The memory controller of claim 9 , wherein application of the nucleation temperature comprises application of multiple separate sub-temperatures for multiple separate sub-periods of time.
14. The memory controller of claim 9 , wherein the second period of time for crystal growth is at least twice as the first period of time for nucleation growth.
15. The memory controller of claim 9 , wherein the memory cell comprises a phase change memory (PCM) cell.
16. A system to implement a phase change set, comprising:
a memory controller; and
a dynamic random access memory (DRAM) device including
a memory array including multiple memory cells of material that changes resistive state based on being in a crystalline state or a non-crystalline state, the memory cells having a thickness to cause a memory cell to be fully amorphized in all active areas of the memory cell in a non-crystalline state, and to lack sufficient crystal nuclei to promote crystal growth; and
interface circuitry coupled to the memory array to control access to the memory cells, including control to change a memory cell from the non-crystalline state to the crystalline state, including application of a nucleation temperature for a first period of time to create crystal nuclei, application of a crystal growth temperature higher than the nucleation temperature for a second period of time to promote crystal growth, and application of a termination temperature lower than the crystal growth temperature for a third period of time to set the crystalline state.
17. The system of claim 16 , wherein the interface circuitry is to control application of the nucleation temperature, the crystal growth temperature, and the termination temperature through control of an amount of current passing through the memory cell.
18. The system of claim 16 , wherein the interface circuitry is further to cause application of an initial temperature prior to the application of the nucleation temperature, the initial temperature higher than the nucleation temperature and higher than the crystal growth temperature.
19. The system of claim 16 , wherein the interface circuitry is to cause application of the nucleation temperature as multiple separate sub-temperatures for multiple separate sub-periods of time.
20. The system of claim 16 , further comprising one or more of:
a processor device on which the memory controller is integrated;
a display communicatively coupled to at least one processor and to the DRAM device;
a battery to power the system; or
a network interface communicatively coupled to at least one processor and to the DRAM device.