Unified semiconductor devices having programmable logic device and heterogeneous memories and methods for forming the same
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a programmable logic device and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.
1. A semiconductor device, comprising:
a first semiconductor structure comprising an array of NAND memory cells and a first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
a third semiconductor structure comprising a programmable logic device and a third bonding layer comprising a plurality of third bonding contacts;
a first bonding interface between the first bonding layer and the third bonding layer, the first bonding contacts being in contact with a first set of the third bonding contacts at the first bonding interface; and
a second bonding interface between the second bonding layer and the third bonding layer, the second bonding contacts being in contact with a second set of the third bonding contacts at the second bonding interface,
wherein the first bonding interface and the second bonding interface are in a same plane.
2. The semiconductor device of claim 1 , wherein the third semiconductor structure comprises:
a substrate;
the programmable logic device on the substrate; and
the third bonding layer above the programmable logic device.
3. The semiconductor device of claim 2 , wherein the first semiconductor structure comprises:
the first bonding layer above the third bonding layer;
the array of NAND memory cells above the first bonding layer; and
a first semiconductor layer above and in contact with the array of NAND memory cells.
4. The semiconductor device of claim 3 , further comprising a first pad-out interconnect layer above the first semiconductor layer, wherein the first semiconductor layer comprises single-crystal silicon or polysilicon.
5. The semiconductor device of claim 2 , wherein the second semiconductor structure comprises:
the second bonding layer above the third bonding layer;
the array of DRAM cells above the second bonding layer; and
a second semiconductor layer above and in contact with the array of DRAM cells.
6. The semiconductor device of claim 5 , further comprising a second pad-out interconnect layer above the second semiconductor layer, wherein the second semiconductor layer comprises single-crystal silicon.
7. The semiconductor device of claim 1 , wherein the first semiconductor structure comprises:
a first substrate;
the array of NAND memory cells on the first substrate; and
the first bonding layer above the array of NAND memory cells.
8. The semiconductor device of claim 7 , wherein the second semiconductor structure comprises:
a second substrate;
the array of DRAM cells on the second substrate; and
the second bonding layer above the array of DRAM cells.
9. The semiconductor device of claim 7 , wherein the third semiconductor structure comprises:
the third bonding layer above the first bonding layer and the second bonding layer;
the programmable logic device above the third bonding layer; and
a third semiconductor layer above and in contact with the programmable logic device.
10. The semiconductor device of claim 1 , wherein
the first semiconductor structure further comprises a peripheral circuit of the array of NAND memory cells;
the second semiconductor structure further comprises a peripheral circuit of the array of DRAM cells; and
the third semiconductor structure further comprises a peripheral circuit of at least one of the array of NAND memory cells or the array of DRAM cells.
11. The semiconductor device of claim 1 , wherein
the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the array of NAND memory cells;
the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of DRAM cells; and
the third semiconductor structure comprises a third interconnect layer vertically between the third bonding layer and the programmable logic device.
12. The semiconductor device of claim 11 , wherein
the programmable logic device is electrically connected to the array of NAND memory cells through the first and third interconnect layers, the first bonding contacts, and the first set of the third bonding contacts;
the programmable logic device is electrically connected to the array of DRAM cells through the second and third interconnect layers, the second bonding contacts, and the second set of the third bonding contacts; and
the array of NAND memory cells is electrically connected to the array of DRAM cells through the first, second, and third interconnect layers and the first, second, and third bonding contacts.
13. The semiconductor device of claim 1 , wherein the programmable logic device comprises a plurality of programmable logic blocks.
14. The semiconductor device of claim 1 , wherein each of the first, second, and third semiconductor structures does not include a static random-access memory (SRAM) cache.
15. A method for forming a semiconductor device, comprising:
forming a plurality of first semiconductor structures on a first wafer, wherein at least one of the first semiconductor structures comprises an array of NAND memory cells and a first bonding layer comprising a plurality of first bonding contacts;
dicing the first wafer into a plurality of first dies, such that at least one of the first dies comprises the at least one of the first semiconductor structures;
forming a plurality of second semiconductor structures on a second wafer, wherein at least one of the second semiconductor structures comprises an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
dicing the second wafer into a plurality of second dies, such that at least one of the second dies comprises the at least one of the second semiconductor structures;
forming a plurality of third semiconductor structures on a third wafer, wherein at least one of the third semiconductor structures comprises a programmable logic device and a third bonding layer comprising a plurality of third bonding contacts;
dicing the third wafer into a plurality of third dies, such that at least one of the third dies comprises the at least one of the third semiconductor structures; and
bonding (i) the third die and (ii) each of the first die and the second die in a face-to-face manner, such that the third semiconductor structure is bonded to each of the first semiconductor structure and the second semiconductor structure, wherein the first bonding contacts are in contact with a first set of the third bonding contacts at a first bonding interface, and the second bonding contacts are in contact with a second set of the third bonding contacts at a second bonding interface.
16. The method of claim 15 , wherein forming the plurality of first semiconductor structures comprises:
forming the array of NAND memory cells on the first wafer;
forming a first interconnect layer above the array of NAND memory cells; and
forming the first bonding layer above the first interconnect layer.
17. The method of claim 15 , wherein forming the plurality of second semiconductor structures comprises:
forming the array of DRAM cells on the second wafer;
forming a second interconnect layer above the array of DRAM cells; and
forming the second bonding layer above the second interconnect layer.
18. The method of claim 15 , wherein forming the plurality of third semiconductor structures comprises:
forming the programmable logic device on the third wafer;
forming a third interconnect layer above the programmable logic device; and
forming the third bonding layer above the third interconnect layer.
19. A method for forming a semiconductor device, comprising:
forming a plurality of first semiconductor structures on a first wafer, wherein at least one of the first semiconductor structures comprises an array of NAND memory cells and a first bonding layer comprising a plurality of first bonding contacts;
dicing the first wafer into a plurality of first dies, such that at least one of the first dies comprises the at least one of the first semiconductor structures;
forming a plurality of second semiconductor structures on a second wafer, wherein at least one of the second semiconductor structures comprises an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
dicing the second wafer into a plurality of second dies, such that at least one of the second dies comprises the at least one of the second semiconductor structures;
forming a plurality of third semiconductor structures on a third wafer, wherein at least one of the third semiconductor structures comprises a programmable logic device and a third bonding layer comprising a plurality of third bonding contacts;
bonding (i) the third wafer and (ii) each of the at least one first die and the at least one second die in a face-to-face manner to form a bonded structure, such that the at least one third semiconductor structure is bonded to each of the first semiconductor structure and the second semiconductor structure, wherein the first bonding contacts are in contact with a first set of the third bonding contacts at a first bonding interface, and the second bonding contacts are in contact with a second set of the third bonding contacts at a second bonding interface; and
dicing the bonded structure into a plurality of dies, wherein at least one of the dies comprises the bonded first, second, and third semiconductor structures.
20. The method of claim 19 , wherein forming the plurality of third semiconductor structures comprises:
forming the programmable logic device on the third wafer;
forming a third interconnect layer above the programmable logic device; and
forming the third bonding layer above the third interconnect layer.