RRAM array having lateral RRAM cells and vertical conducting structures

1. An RRAM array, comprising:

a plurality of horizontal electrode lines elongated in a horizontal direction;

a plurality of conducting structures elongated in a vertical direction, wherein each of the conducting structures comprises a plurality of electrode blocks and a plurality of contact vias which are alternately arranged, and wherein the electrode blocks and the electrode lines are on a same horizontal plane; and

a plurality of resistance variable elements sandwiched between the electrode lines and the electrode blocks.

2. The RRAM array as claimed in claim 1 , wherein the electrode blocks are periodically elongated with a substantially constant gap therebetween in the horizontal direction.

3. The RRAM array as claimed in claim 1 , wherein each of the electrode blocks is in a shape of a cube, cuboid, an island, an ellipsoid, or a combination thereof.

4. The RRAM array as claimed in claim 1 , wherein top surfaces of the electrode blocks, the electrode lines and the resistance variable elements are substantially coplanar.

5. The RRAM array as claimed in claim 1 , wherein the electrode lines are bit lines, and the conducting structures are word lines.

6. The RRAM array as claimed in claim 1 , wherein the electrode lines are word lines, and the conducting structures are bit lines.

7. An RRAM array, defined by rectangular coordinates having x, y and z directions, wherein the RRAM array comprises:

a plurality of vertical stacking sets stacked to each other in the z-direction, wherein each of the vertical stacking sets comprises a first layer structure and a second layer structure thereon, wherein the first layer structure comprises:

a plurality of electrode lines and a plurality of the electrode blocks alternately arranged and separated from each other in an x-y plane;

a resistance variable material filling into gaps between the electrode lines and the electrode blocks;

wherein the second layer structure comprises:

an insulation layer on the first layer structure; and

a plurality of contact vias within the insulation layer and aligned to the electrode blocks.

8. The RRAM array as claimed in claim 7 , wherein the electrode blocks and the contact vias of the vertical stacking sets form a plurality of conducting structures which is elongated in the z-direction.

9. The RRAM array as claimed in claim 7 , wherein the electrode lines are continuously elongated in the x-direction, and the electrode blocks are periodically arranged with a substantially constant gap therebetween in the x-direction.

10. The RRAM array as claimed in claim 9 , wherein the electrode lines and the electrode blocks are alternately arranged with a substantially constant distance from the electrode blocks to adjacent electrode lines in the y-direction.

11. The RRAM array as claimed in claim 10 , wherein the substantially constant distance is in a range from about 5 nm to about 300 nm.

12. The RRAM array as claimed in claim 10 , wherein the widths of electrode blocks and the electrode lines in the y-direction are substantially equal to the substantially constant distance.

13. The RRAM array as claimed in claim 7 , wherein portions of the resistance variable material between the electrode blocks and the electrode lines in the y-direction construct a plurality of lateral RRAM cells of the RRAM array with the electrode blocks and the electrode lines.

14. The RRAM array as claimed in claim 7 , wherein the resistance variable material comprises titanium oxide, nickel oxide, hafnium oxide, zirconium oxide, tungsten oxide, zinc oxide, aluminum oxide, tantalum oxide, molybdenum oxide, Ge 2 Sb 2 Te 5 , AgInSbTe, SrTiO 3 , ZrTiO 3 , Pr 0.7 Ca 0.3 MnO 3 , GeS, GeSe, Cu 2 S, copper 7,7,8,8-tetracyanoquinodimethane (CuTCNQ) or a combination thereof.

15. The RRAM array as claimed in claim 7 , wherein each of the electrode blocks is in the shape of a cube, cuboid, an island, an ellipsoid, or a combination thereof.

16. The RRAM array as claimed in claim 7 , wherein the insulation layer comprises silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials or a combination thereof.

17. A method for fabricating an RRAM array, comprising:

(a) forming a first layer structure, wherein the first layer structure comprises a plurality of electrode lines and a plurality of electrode blocks separated from each other and a resistance variable material filling into the gaps between the electrode blocks and the electrode lines;

(b) forming a second layer structure on the first layer structure, wherein the second layer structure comprises an insulation layer and a plurality of contact vias within the insulation layer and aligned to the electrode blocks; and

(c) repeating steps (a) and (b) to form resultant layer structures.

18. The method as claimed in claim 17 , wherein the step (a) comprises:

depositing a metal layer over a substrate or another insulation layer;

patterning the metal layer by a lithography technique to form the electrode blocks and the electrode lines;

depositing the resistance variable material over the substrate and the another insulation layer; and

removing a portion of the resistance variable material above the electrode blocks and the electrode lines.

19. The method as claimed in claim 17 , wherein the step (a) comprises:

depositing the resistance variable material over the substrate or another insulation layer;

patterning the resistance variable material by a lithography technique such that the resistance variable material has hollow portions that have patterns corresponding to the patterns of electrode blocks and the electrode lines;

depositing a metal layer over the substrate or the another insulation layer to form the electrode blocks and the electrode lines; and

removing a portion of the metal layer above the resistance variable material.

20. The method as claimed in claim 17 , wherein the step (b) comprises:

forming the insulation layer on the first layer structure;

forming a plurality of openings exposing the electrode blocks; and

depositing a conductive material into the openings to form the contact vias.