Wafer level integration including design/co-design, structure process, equipment stress management and thermal management
A multi-layer wafer and method of manufacturing such wafer are provided. The method includes applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.
1. A multi-layer wafer comprising:
two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer, the polymer layer having a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition, the two heterogeneous wafers low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.
2. The multi-layer wafer of claim 1 , wherein the stress compensating polymer layer comprises at least one of a thermal plastic, an adhesive composition or co-polymer having adhesion.
3. The multi-layer wafer of claim 1 , further comprising islands of heterogeneous material in at least one heterogeneous wafer.
4. The multi-layer wafer of claim 3 , further comprising:
channels between the islands of heterogeneous material; and
one of an oxide or a polymer channel deposition to fill the channels.
5. The multi-layer wafer of claim 4 , wherein the channels are back filled with one of oxide or polymer to create a channel oxide deposition.
6. The multi-layer wafer of claim 1 , wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si, CMOS and glass, CMOS and sapphire, CMOS and SiC on Si, CMOS and diamond on Si, or CMOS and sapphire on Si.
7. The multi-layer wafer of claim 1 , wherein the stress compensating polymer layer has a thickness determined by a viscosity of a liquid polymer applied to the at least one of the two heterogeneous wafers and a spin speed.
8. The multi-layer wafer of claim 1 , wherein the stress compensating polymer layer comprises a free-standing sheet of dry polymer film bonded to the least one heterogeneous wafer.
9. The multi-layer wafer of claim 1 , further comprising a promoter added to at least one of the heterogeneous wafers or the stress compensating polymer layer.
10. The multi-layer wafer of claim 1 , the stress compensating polymer layer is UV cured.
11. The multi-layer wafer of claim 1 , wherein at least one of the heterogeneous wafers of the multi-layer wafer pair is thinned.
12. The multi-layer wafer of claim 1 , further comprising interconnection vias between the two heterogeneous wafers of the multi-layer wafer pair.
13. The multi-layer wafer of claim 1 , wherein the multi-layer wafer pair is low temperature bonded to at least one other multi-layer wafer pair to form a multi-layer wafer stack.
14. The multi-layer wafer of claim 1 , wherein the two heterogeneous wafers are low temperature bonded at a temperature range of room temperature to 100° C.
15. The multi-layer wafer of claim 1 , wherein the functionality is greater than or equal to 2 acrylates/molecule.