IP Library › Granted Patent US 10,673,225
Granted Patent B2
US 10,673,225 · App. 15/274,469 · Granted Jun 2, 2020

Electrical receptacle fault protection

Inventors: John Eriksen (Ontario, CA); Jean-Guy Gagne (Etobicoke, CA); James W. Rogers (Toronto, CA); Patrick Belanger (British Columbia, CA); Rene K. Pardo (Richmond Hill, CA)
Assignee: Brainwave Research Corporation
H02H3/00H01R13/7135H01R24/78H02H9/042H02H11/002H01R2103/00
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Quick Facts
Patent No.
US 10,673,225
App. No.
15/274,469
Granted
Jun 2, 2020
Kind
B2
Abstract

An electrical receptacle contains a plug outlet that has a pair of contacts for electrical connection to respective hot and neutral power lines. A controlled switch, such as a TRIAC, is connected in series relationship between the outlet contact and the hot power line. Sensors in the receptacle outputs signals to a processor having an output coupled to the control terminal of the controlled switch. The processor outputs an activation signal or a deactivation signal to the controlled switch in response to received sensor signals that are indicative of conditions relative to the first and second contacts.

Claims (19)

1. A system comprising:

a plurality of electrical receptacles coupled to hot and neutral power lines;

a first said electrical receptacle comprising:

a plug outlet comprising a contact configured for electrical connection to the hot power line;

a communication subsystem configured to communicate with a downstream load and/or a second said electrical receptacle which is downstream to said first said electrical receptacle;

a processor configured to sample signals at said plug outlet and sample signals downstream of the first electrical receptacle and, in response to the sampled signals satisfying criteria, outputting a deactivation signal to the communication subsystem for deactivation of said second receptacle from the hot line.

2. A system as recited in claim 1 , wherein the criteria includes a threshold for the sum of current of the plug outlet and current downstream to the electrical receptacle.

3. A system as recited in claim 1 , wherein the criteria includes a threshold for current downstream of the electrical receptacle.

4. A system as recited in claim 1 , wherein the output deactivation signal is not applied to control of said plug outlet.

5. A system as recited in claim 1 , wherein said second receptacle comprises a second plug outlet, said first and second plug outlets comprise, respectively, a controlled switch for serial connection to the hot line, and said processor is configured to wait a specified delay prior to outputting said deactivation signal.

6. A system as recited in claim 5 , wherein said processor is configured to, after the specified delay and after determining that the deactivating was not performed by the downstream load and/or the second receptacle, deactivate at least one of the respective switches.

7. A system as recited in claim 1 , wherein the downstream electrical connection is wired in parallel from the plurality of power lines with respect to said plug outlet.

8. A system comprising:

a plurality of electrical receptacles coupled to hot and neutral power lines;

a first said electrical receptacle comprising:

a plug outlet comprising a contact configured for electrical connection to the hot power line;

a communication subsystem configured to communicate with a downstream load and/or a second said electrical receptacle which is downstream to said first said electrical receptacle;

a processor configured to sample signals at said plug outlet and sample signals downstream of the first electrical receptacle and, in response to the sampled signals satisfying criteria, outputting a deactivation signal to the communication subsystem for deactivation of said second receptacle from the hot line,

wherein the processor is further configured to determine that occurrence of a fault at an input of said first receptacle and, in response thereto, to wait a second specified delay of a period shorter than said specified delay, to output a deactivation signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2016
From: ERIKSEN, JOHN; GAGNE, JEAN-GUY; ROGERS, JAMES W.; BELANGER, PATRICK; PARDO, RENE K.
To: BRAINWAVE RESEARCH CORPORATION
Reel/Frame 039851/0723 →
Continuity (4)
Provisional Application 62222904 · Sep 24, 2015
Provisional Application 62366910 · Jul 26, 2016
Provisional Application 62377962 · Aug 22, 2016
Related Publication 20170104325A1 · Apr 13, 2017
Cited By (2)
US 12,217,596 US 12,482,622