IP Library Granted Patent US 10,079,256
Granted Patent B2
US 10,079,256 · App. 15/274,921 · Granted Sep 18, 2018

Image sensor pixels with light guides and light shield structures

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Quick Facts
Patent No.
US 10,079,256
App. No.
15/274,921
Granted
Sep 18, 2018
Kind
B2
Abstract

A front-side illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode, transistor gate structures, shallow trench isolation structures, and other associated pixel circuits formed in a semiconductor substrate. Buried light shielding structures that are opaque to light may be formed over regions of the substrate to prevent the transistor gate structures, shallow trench isolation structures, and the other associated pixel circuits from being exposed to stray light. Buried light shielding structures formed in this way can help reduce optical pixel crosstalk.

Claims (46)

1. An image sensor, comprising:

a substrate;

first and second adjacent photodiodes formed in the substrate;

a floating diffusion node that is formed between the first and second photodiodes;

a buried light shield structure that is formed on top of the substrate over the floating diffusion node, wherein the buried light shield structure has an elongated horizontal segment that extends parallel to the surface of the substrate and an elongated vertical segment that extends perpendicular to the surface of the substrate;

a shallow trench isolation structure that is formed in the substrate between the first and second photodiodes and that is covered by the buried light shield structure; and

a dielectric stack formed on the substrate, wherein the dielectric stack includes interconnect routing structures that are formed over the buried light shield structure, wherein the buried light shield structure is formed in the dielectric stack.

2. The image sensor defined in claim 1 , comprising:

a transistor gate structure that is formed on the substrate between the first and second photodiodes and that is covered by the buried light shield structure.

3. The image sensor defined in claim 2 , wherein the transistor gate structure has a top surface and a side surface, wherein the elongated horizontal segment extends parallel to the top surface, and wherein the elongated vertical segment extends parallel to the side surface.

4. The image sensor defined in claim 2 , comprising:

antireflective coating material formed over the first and second photodiodes and the transistor gate structure.

5. The image sensor defined in claim 1 , further comprising:

a first light guide formed in the dielectric stack over the first photodiode; and

a second light guide formed in the dielectric stack over the second photodiode.

6. The image sensor defined in claim 1 , wherein the elongated vertical segment of the buried light shield structure has two vertical surfaces and extends from an end of the elongated horizontal segment of the buried light shield structure.

7. A method of fabricating an image sensor, comprising:

forming first and second neighboring photodiodes in a substrate, wherein the first and second photodiodes are adjacent to a surface of the substrate;

forming first and second light guide structures directly above the first and second photodiodes;

forming a light shielding structure on the substrate between the first and second photodiodes and between the first and second light guide structures; and

forming a transistor gate structure on the substrate that is covered by the light shielding structure.

8. The method defined in claim 7 , further comprising:

forming a pixel isolation structure in the substrate that is covered by the light shielding structure.

9. The method defined in claim 7 , further comprising:

forming an antireflective coating liner on the transistor gate structure and on the first and second photodiodes.

10. The method defined in claim 7 , wherein forming the lighting shielding structure comprises forming a tungsten buried light shield.

11. The method defined in claim 7 , further comprising:

forming a dielectric stack on the substrate, wherein the dielectric stack includes interconnect routing structures that are formed directly over the light shielding structure.

12. The method defined in claim 11 , wherein forming first and second light guide structures directly above the first and second photodiodes comprises:

forming first and second light guide structures within the dielectric stack.

13. A system, comprising:

a central processing unit;

memory;

a lens;

input-output circuitry; and

an imaging device, wherein the imaging device comprises:

a front-side illuminated image sensor having a plurality of photosensitive elements formed in a substrate;

buried light shields formed on regions of the substrate between each pair of adjacent photosensitive elements;

transistor gate structures that are covered by the buried light shields; and

adsorptive antireflective coating material interposed between the buried light shields and the transistor gate structures.

14. The system defined in claim 13 , wherein the plurality of photosensitive elements comprises a plurality of photodiodes.

15. The system defined in claim 13 , wherein the transistor gate structures are covered by the buried light shields on at least three sides.

16. The system defined in claim 15 , wherein the image sensor further comprises:

shallow trench isolation structures that are covered by the buried light shields.

17. The system defined in claim 16 , wherein the absorptive antireflective coating material is formed over the photosensitive elements and the transistor gate structures and not over the buried light shields.

18. The system defined in claim 17 , wherein the absorptive antireflective coating material is formed at a region that is non-overlapping with the shallow trench isolation structures.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 041187, FRAME 0295 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064151/0203 →
SECURITY INTEREST Recorded Dec 23, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 041187/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2016
From: LENCHENKOV, VICTOR; CAO, DONGQING
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 039848/0383 →