Semiconductor device and method of forming the semiconductor device
A method of forming a semiconductor device, includes forming first and second SiGe fins on a substrate, forming a protective layer on the first SiGe fin, forming a germanium-containing layer on the second SiGe fin and on the protective layer on the first SiGe fin, and performing an anneal to react the germanium-containing layer with a surface of the second SiGe fin.
1. A method of forming a semiconductor device, the method comprising:
forming first and second SiGe fins including a first amount of Ge on a substrate;
forming a protective layer on the first SiGe fin;
forming a germanium-containing layer on the second SiGe fin and on the protective layer on the first SiGe fin; and
performing an anneal to react the germanium-containing layer with a surface of the second SiGe fin, such that a central portion of the second SiGe fin includes the first amount of Ge, and the surface of the second SiGe fin includes a second amount of Ge greater than the first amount,
wherein in the performing of the anneal, the protective layer inhibits a reaction between the germanium-containing layer and a surface of the first SiGe fin.
2. The method of claim 1 , wherein a temperature in the performing of the anneal is no greater than 700° C., and the anneal is performed in a nitrogen ambient.
3. The method of claim 1 , wherein the performing of the anneal comprises reacting the germanium-containing layer with the surface of the second SiGe fin such that the surface of the second SiGe fin comprises a Ge-rich SiGe surface.
4. The method of claim 3 , wherein the Ge-rich SiGe surface of the second SiGe fin comprises at least 40% Ge, and the central portion of the second SiGe fin comprises no more than 20% Ge.
5. The method of claim 3 , wherein a Ge content of the Ge-rich SiGe surface of the second SiGe fin is at least 20% greater than a Ge content of the central portion of the second SiGe fin.
6. The method of claim 5 , wherein the Ge content of the central portion of the second SiGe fin is substantially equal to a Ge content of the first SiGe fin.
7. The method of claim 3 , wherein a thickness of the Ge-rich SiGe surface is in a range from 1 nn to 4 nm.
8. The method of claim 1 , wherein a thickness of the germanium-containing layer is in a range from 1 nn to 4 nm.
9. The method of claim 1 , wherein the germanium-containing layer comprises a GeO 2 layer, and in the performing of the anneal, the GeO 2 layer reacts with germanium and silicon in the surface of the second SiGe fin according to the following two reactions:
Ge+GeO 2 →2GeO, and
Si+GeO 2 →Ge+SiO 2 .
10. The method of claim 1 , further comprising:
after the performing of the anneal, removing an unreacted portion of the germanium-containing layer and the protective layer.
11. The method of claim 10 , wherein the removing of the unreacted portion of the germanium-containing layer and the protective layer comprises using diluted HF to remove the unreacted portion of the germanium-containing layer and the protective layer.
12. The method of claim 1 , wherein the device comprises an nFET and a pFET, and the first SiGe fin comprises a fin of the nFET fin and the second SiGe fin comprises a fin of the pFET,
wherein the fin of the nFET comprises a tensile strain, and
wherein after the performing of the anneal, the fin of the pFET comprises a compressive strain in a vertical direction of at least 1 Gpa.
13. The method of claim 1 , further comprising:
forming a bottom source/drain (S/D) region and a bottom spacer on the substrate, the first and second SiGe fins being formed on the bottom S/D region.
14. The method of claim 1 , wherein the protective layer comprises SiO 2 .
15. The method of claim 1 , wherein the forming of the germanium-containing layer comprises depositing GeO 2 by atomic layer deposition (ALD).
16. A method of forming a semiconductor device, the method comprising:
forming a first SiGe fin on a substrate on an nFET side of the semiconductor device, the first SiGe fin comprising a first amount of Ge;
forming a second SiGe fin on the substrate on a pFET side of the semiconductor device, the second SiGe fin comprising a second amount of Ge which is substantially equal to the first amount;
forming a protective layer on the first SiGe fin;
forming a germanium-containing layer on the second SiGe fin and on the protective layer on the first SiGe fin; and
performing an anneal to react the germanium-containing layer with a surface of the second SiGe fin such that a central portion of the second SiGe fin includes the first amount of Ge and the surface of the second SiGe fin comprises a third amount of Ge which is at least 20% greater than the second amount, a temperature of the anneal being no greater than 700° C., and the anneal being performed in a nitrogen ambient,
wherein after the performing of the anneal, the second SiGe fin comprises a compressive strain in a vertical direction of at least 1Gpa, and
wherein in the performing of the anneal, the protective layer inhibits a reaction between germanium-containing layer and a surface of the first SiGe fin.