Instruction and logic for early underflow detection and rounder bypass

1. A processor for floating point underflow detection, comprising:

circuitry to decode a first instruction, the first instruction when executed by the processor is to perform a fused multiply-add (FMA) operation; and

a floating point unit including circuitry to:

determine a non-normalized result of the first instruction based on a first input, a second input, and a third input;

determine whether underflow exists in the non-normalized result based on a first exponent of the first input, a second exponent of the second input, and a third exponent of the third input;

determine an unrounded normalized result and an unrounded result bypass extension based on the non-normalized result; and

route the unrounded normalized result and the unrounded result bypass extension via a bypass path to the floating point unit for a second instruction, the second instruction when executed by the processor is to perform another FMA operation.

2. The processor of claim 1 , wherein the first instruction includes a subtraction operation.

3. The processor of claim 1 , wherein the first instruction includes an addition operation, the addition operation including a subtraction.

4. The processor of claim 1 , wherein the circuitry to determine whether underflow exists in the non-normalized result includes circuitry to:

determine whether positive underflow exists in the non-normalized result; and

determine whether negative underflow exists in the non-normalized result.

5. The processor of claim 1 , wherein the circuitry to determine whether underflow exists includes circuitry to determine whether early underflow detection is enabled.

6. The processor of claim 1 , wherein the circuitry to determine the unrounded normalized result and the unrounded result bypass extension includes circuitry to determine whether rounder bypass is enabled.

7. At least one non-transitory machine readable storage medium, comprising computer-readable instructions carried on the machine readable storage medium, the instructions readable by a hardware processor, the instructions, when read and executed, for causing the processor to perform:

decoding a first instruction, the first instruction when executed is for performing a fused multiply-add (FMA) operation;

determining a non-normalized result of the first instruction based on a first input, a second input, and a third input;

determining whether underflow exists in the non-normalized result based on a first exponent of the first input, a second exponent of the second input, and a third exponent of the third input;

determining an unrounded normalized result and an unrounded result bypass extension based on the non-normalized result; and

routing the unrounded normalized result and the unrounded result bypass extension via a bypass path for a second instruction, the second instruction when executed is for performing another FMA operation.

8. The at least one non-transitory machine readable storage medium of claim 7 , wherein the first instruction includes a subtraction operation.

9. The at least one non-transitory machine readable storage medium of claim 7 , wherein the first instruction includes an addition operation, the addition operation including a subtraction.

10. The at least one non-transitory machine readable storage medium of claim 7 , wherein the instructions for causing the processor to perform determining whether underflow exists in the non-normalized result further comprise instructions for causing the processor to perform:

determining whether positive underflow exists in the non-normalized result; and

determining whether negative underflow exists in the non-normalized result.

11. The at least one non-transitory machine readable storage medium of claim 7 , wherein the instructions for causing the processor to perform determining whether underflow exists further comprise instructions for causing the processor to perform determining whether early underflow detection is enabled.

12. A floating point unit for underflow detection, comprising circuitry to:

determine a non-normalized result of a first fused multiply-add (FMA) operation based on a first input, a second input, and a third input;

determine whether underflow exists in the non-normalized result based on a first exponent of the first input, a second exponent of the second input, and a third exponent of the third input;

determine an unrounded normalized result and an unrounded result bypass extension based on the non-normalized result; and

route the unrounded normalized result and the unrounded result bypass extension via a bypass path to the floating point unit for a second FMA operation to be performed by the floating point unit.

13. The floating point unit of claim 12 , wherein the first FMA operation includes a subtraction operation.

14. The floating point unit of claim 12 , wherein the first FMA operation includes an addition operation, the addition operation including a subtraction.

15. The floating point unit of claim 12 , wherein the circuitry to determine whether underflow exists in the non-normalized result includes circuitry to:

determine whether positive underflow exists in the non-normalized result; and

determine whether negative underflow exists in the non-normalized result.

16. The floating point unit of claim 12 , wherein the circuitry to determine whether underflow exists includes circuitry to determine whether early underflow detection is enabled.

17. The floating point unit of claim 12 , wherein the circuitry to determine the unrounded normalized result and the unrounded result bypass extension includes circuitry to determine whether rounder bypass is enabled.