Fabrication of single or multiple gate field plates
A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
1. A high electron mobility transistor (HEMT), comprising:
a spacer layer directly on an active region; and
source and drain electrodes making ohmic contacts with the active region;
wherein the spacer layer is etched to expose the active region and a gate electrode is deposited such that at least a bottom portion of the gate electrode is directly on the active region,
wherein a field plate extends a distance across at least a portion of the spacer layer and towards the drain electrode;
wherein a second spacer layer comprising silicon nitride is on the field plate and at least a portion of the spacer layer;
wherein a second field plate is on the second spacer layer; and
wherein a power added efficiency of the HEMT is increased as compared to a HEMT without the field plate.
2. The transistor of claim 1 , wherein:
the active region comprises a barrier layer directly on a channel layer, and
the spacer layer is directly on the barrier layer.
3. A device, comprising:
an active region;
a first spacer layer directly on the active region;
a gate electrode directly on the active region;
a first field plate connected to the gate electrode and on the first spacer layer;
a second spacer layer on the first field plate; and
a second field plate on the second spacer layer, the second field plate overlapping with the first field plate; and
wherein none of the first spacer layer is removed to expose the active region.
4. The device of claim 3 , wherein the spacer layers comprise silicon nitride.
5. The device of claim 3 , wherein the spacer layers comprise a dielectric.
6. The device of claim 3 , wherein the first spacer layer comprises a semiconductor.
7. The device of claim 6 , wherein the semiconductor is undoped or depleted.
8. The device of claim 3 , wherein the active region comprises a barrier layer directly on a channel layer and the spacer layer is directly on the barrier layer.
9. A transistor, comprising:
a semiconductor layer comprising a barrier layer on a channel layer;
a spacer layer directly on the barrier layer, wherein the spacer layer includes an opening;
a gate deposited in the opening and directly on a surface of the barrier layer;
a source contact on the barrier layer in a source contact region and a drain contact on the barrier layer in a drain contact region; and
a field plate on the spacer layer, wherein the spacer layer is not removed to expose the barrier layer except in the opening, the source contact region, and the drain contact region, so that the spacer layer is in direct contact with the barrier layer across an entire length between the source contact and the gate and across an entire length between the drain contact and the gate.
10. The transistor of claim 9 , further comprising:
a second spacer layer on the field plate; and
a second field plate on the second spacer layer.
11. The transistor of claim 9 , wherein:
the transistor further comprises the barrier layer directly on the channel layer, and
the field plate extends a distance away from the gate towards the drain electrode and further comprising a passivation layer on the gate and at least a portion of the spacer layer.
12. The transistor of claim 9 , wherein the spacer layer comprises a dielectric.