TrenchMOS
A device is disclosed. The device comprises a substrate having an epitaxial layer of a first conductivity type, a deep trench of a first depth, a pillar region of a second conductivity type of a second depth and a blocking layer of a third conductivity type immediately below a bottom surface of the deep trench. The second depth is larger than the first depth.
1. A device, comprising:
a substrate having an epitaxial layer of a first conductivity type;
a deep trench of a first depth;
a pillar region of a second conductivity type of a second depth, wherein the second depth is larger than the first depth; and
a blocking layer of a third conductivity type immediately below bottom surface of the deep trench,
wherein the first conductivity type is n-type, the second conductivity type is p-type and the third conductivity type is n+ type.
2. The device of claim 1 , wherein the blocking layer has an area that is approximately the same as an area of the bottom surface of the deep trench.
3. The device of claim 1 , wherein the deep trench has an area that is partially filled with a gate oxide layer.
4. The device of claim 3 , wherein the deep trench has side walls that are covered with a gate oxide layer.
5. The device of claim 4 , wherein the deep trench has a remaining empty area that is filled with a polysilicon material to form a gate electrode.
6. The device of claim 5 , further including a dielectric layer over the gate electrode.
7. The device of claim 1 , further including a body region on an upper portion of the pillar region.
8. The device of claim 7 , further including a source region above the body region.
9. The device of claim 1 , wherein the blocking layer is formed using arsenic implantation.
10. The method of claim 1 , further including forming a dielectric layer over the polysilicon material.
11. The method of claim 1 , wherein the pillar is formed through boron implantation.
12. The method of claim 1 , wherein the epitaxial layer is formed using phosphorous implantation.
13. The method of claim 1 , wherein prior to filling the remaining area of the deep trench with the polysilicon material, side walls of the deep trench are covered with a gate oxide.
14. A process of manufacturing a device, the process comprising:
forming an epitaxial layer of a first conductivity type on in a substrate;
forming a deep trench using a layer of a hard mask;
implanting a blocking layer of a second conductivity type at a bottom of the deep trench;
partially filling an area the deep trench with a gate oxide;
filling a remaining area of the deep trench with a polysilicon material;
forming a pillar of a third conductivity type, wherein the pillar is larger in height that the deep trench on one side of the deep trench; and
forming a body region over the pillar and a source region over the body region,
wherein the first conductivity type is n-type, the second conductivity type is p-type and the third conductivity type is n+ type.
15. The method of claim 14 , wherein the blocking layer is formed using arsenic implantation.
16. The method of claim 14 , wherein the hard mask is formed using silicon nitride.
17. The method of claim 15 , wherein the pillar is formed through an implantation process such that a portion of an area over the deep trench is exposed for implantation.