Information processing device and method executed by an information processing device

1. An information processing device comprising:

a first memory; and

a processor coupled to the first memory and configured to:

transmit a first request requesting a second memory to send first data,

receive the first data from the second memory,

transmit a second request requesting a third memory to send second data,

receive the second data from the third memory,

store the first data and the second data in the first memory,

specify a first latency that is a time from when the second memory receives the first request to when the second memory sends the first data to the information processing device, and a second latency that is a time from when the third memory receives the second request to when the third memory sends the second data to the information processing device,

specify a first access frequency from the information processing device to the second memory, and a second access frequency from the information processing device to the third memory,

select one of the first data and the second data based on a first ratio of a first value to a second value and a second ratio of a first data volume of the first data stored in the first memory to a second data volume of the second data stored in the first memory, the first value being obtained by multiplying the first latency and the first access frequency, and the second value being obtained by multiplying the second latency and the second access frequency, and

delete, from the first memory, at least a part of the selected first data or at least a part of the selected second data.

2. The information processing device according to claim 1 , wherein the processor is further configured to:

obtain third data from one of the second memory and the third memory, and

store the third data in the first memory after the part of the selected first data or the part of the selected second data is deleted from the first memory.

3. The information processing device according to claim 2 , wherein the processor is configured to:

when free space of the first memory is less than a third data volume of the third data, delete the part of the selected first data or the part of the selected second data from the first memory.

4. The information processing device according to claim 1 , wherein the processor is further configured to:

compare the first ratio with the second ratio, and thereby to select one of the first data and the second data.

5. The information processing device according to claim 1 , wherein the processor is further configured to:

count a number of times of access to the second memory and count a number of times of access to the third memory.

6. The information processing device according to claim 1 , wherein the processor is configured to:

when the first data is selected, select data, as the part of the selected first data, which has not been used for arithmetic processing by the processor for a longest time among the first data stored in the first memory, and, when the second data is selected, select data, as the part of the selected second data, which has not been used for arithmetic processing by the processor for a longest time among the second data stored in the first memory.

7. The information processing device according to claim 1 , wherein the processor is further configured to:

when the first latency changes with time, calculate an average value of the first latency, and

when the second latency changes with time, calculate an average value of the second latency.

8. The information processing device according to claim 2 , further comprising:

a cache memory including the first memory and the processor, wherein

the second memory and the third memory are main memories coupled to the information processing device.

9. An information processing device comprising:

a cache memory configured to store data read from a plurality of main memories with different latencies each of which is a time from reception of a data read request until transmission of data; and

a processor coupled to the cache memory and configured to:

specify, for each of the main memories, the latency,

specify, for each of the main memories, an access frequency from the information processing device to each of the main memories,

specify, for each of the main memories, a first value by multiplying the latency and the access frequency,

specify, for each of the main memories, a volume of data that is stored in each of the main memories and that is stored in the cache memory, and

delete, from the cache memory, at least a part of the data stored in the cache memory based on the first value and the volume of the data.

10. A method executed by an information processing device including a first memory, the method comprising:

transmitting a first request requesting a second memory to send first data;

receiving the first data from the second memory;

transmitting a second request requesting a third memory to send second data;

receiving the second data from the third memory;

storing the first data and the second data in the first memory;

specifying a first latency that is a time from when the second memory receives the first request to when the second memory sends the first data to the information processing device, and a second latency that is a time from when the third memory receives the second request to when the third memory sends the second data to the information processing device;

specifying a first access frequency from the information processing device to the second memory, and a second access frequency from the information processing device to the third memory;

selecting one of the first data and the second data based on a first ratio of a first value to a second value and a second ratio of a first data volume of the first data stored in the first memory to a second data volume of the second data stored in the first memory, the first value being obtained by multiplying the first latency and the first access frequency, and the second value being obtained by multiplying the second latency and the second access frequency; and

deleting, from the first memory, at least a part of the selected first data or at least a part of the selected second data.

11. The method according to claim 10 , further comprising:

obtaining third data from one of the second memory and the third memory; and

storing the third data in the first memory after the part of the selected first data or the part of the selected second data is deleted from the first memory.

12. The method according to claim 11 , wherein

the deleting is executed when free space of the first memory is less than a third data volume of the third data.

13. The method according to claim 10 , further comprising:

comparing the first ratio with the second ratio, wherein

the selecting is executed based on the comparing.

14. The method according to claim 10 , further comprising:

counting a number of times of access to the second memory; and

counting a number of times of access to the third memory.

15. The method according to claim 10 , further comprising:

when the first data is selected, selecting data, as the part of the selected first data, which has not been used for arithmetic processing by the processor for a longest time among the first data stored in the first memory, and, when the second data is selected, selecting data, as the part of the selected second data, which has not been used for arithmetic processing by the processor for a longest time among the second data stored in the first memory.

16. The method according to claim 10 , further comprising:

when the first latency changes with time, calculating an average value of the first latency; and

when the second latency changes with time, calculating an average value of the second latency.

17. The method according to claim 11 , wherein:

the information processing device includes a cache memory including the first memory and the processor, and

the second memory and the third memory are a main memory coupled to the information processing device.