Semiconductor device and method of forming the same

1. A semiconductor device, comprising:

a substrate ( 102 ), having a first voltage area ( 102 A) and a second voltage area ( 102 B);

a shallow trench isolation (STI) structure ( 200 ) located in the substrate ( 102 ), wherein a first portion ( 200 A) of the STI structure ( 200 ) is located in the first voltage area ( 102 A), a second portion ( 200 B) of the STI structure ( 200 ) is located in the second voltage area ( 102 B) and a bottom surface (BS 1 ) of the first portion ( 200 A) of the STI structure ( 200 ) in the first voltage area ( 102 A) is lower than a bottom surface (BS 2 ) of the second portion ( 200 B) of the STI structure ( 200 ) in the second voltage area ( 102 B);

a first gate oxide layer (GO 1 ) located on the substrate ( 102 ) in the first voltage area ( 102 A), wherein a top surface (TS) of the STI structure ( 200 ), a top surface (OLT) of the first gate oxide layer (GO 1 ) and a top surface ( 102 T) of the substrate ( 102 ) in the second voltage area ( 102 B) are substantially coplanar to generate a coplanar surface ( 102 T/TS/OLT);

a second gate oxide layer (GO 2 ) located on the first gate oxide layer (GO 1 ); and

a first gate structure ( 310 ) located on the second gate oxide layer (GO 2 ) in the first voltage area ( 102 A).

2. The semiconductor device according to claim 1 , wherein the second gate oxide layer (GO 2 ) is located on the substrate ( 102 ) in the second voltage area ( 102 B), and the semiconductor device further comprises:

a second gate structure ( 320 ) located on the second gate oxide layer (GO 2 ) in the second voltage area ( 102 B).

3. The semiconductor device according to claim 1 , wherein a bottom surface of the first gate oxide layer (GO 1 ) is located below the coplanar surface ( 102 T/TS/OLT).

4. The semiconductor device according to claim 1 , wherein an operating voltage of the first voltage area ( 102 A) is from 6V to 8V.

5. The semiconductor device according to claim 1 , wherein an operating voltage of the second voltage area ( 102 B) is from 0.9V to 1V.

6. The semiconductor device according to claim 1 , wherein a material of the second gate oxide layer (GO 2 ) is HfO 2 .

7. The semiconductor device according to claim 2 , wherein a material of the second gate oxide layer (GO 2 ) is HfO 2 .

8. A method of forming a semiconductor device, comprising:

providing a substrate ( 102 ) having a first voltage area ( 102 A) and a second voltage area ( 102 B);

forming a first oxide layer (OL 1 ) in the first voltage area ( 102 A), wherein the first oxide layer (OL 1 ) grows up and down from a top surface ( 102 T) of the substrate ( 102 ) in the first voltage area ( 102 A), and is not formed in the second voltage area ( 102 B);

removing the first oxide layer (OL 1 ) to form a recess (H 1 ) in the first voltage area ( 102 A); and

forming a shallow trench isolation (STI) structure ( 200 ) in the substrate ( 102 ), wherein a first portion ( 200 A) of the STI structure ( 200 ) is located in the first voltage area ( 102 A) and a second portion ( 200 B) of the STI structure ( 200 ) is located in the second voltage area ( 102 B), a top surface (TS) of the STI structure ( 200 ) is higher than the top surface ( 102 T) of the substrate ( 102 ), and a bottom surface (BS 1 ) of the first portion ( 200 A) of the STI structure ( 200 ) in the first voltage area ( 102 A) is lower than a bottom surface (BS 2 ) of the second portion ( 200 B) of the STI structure ( 200 ) in the second voltage area ( 102 B).

9. The method of forming the semiconductor device according to claim 8 , wherein prior to forming the first oxide layer (OL 1 ), a first mask layer ( 104 ) is formed on the substrate ( 102 ) in the second voltage area ( 102 B), and a thermal oxidation process is used to form the first oxide layer (OL 1 ) in the first voltage area ( 102 A).

10. The method of forming the semiconductor device according to claim 9 , wherein prior to forming the STI structure ( 200 ), a second mask layer ( 106 ) is formed on the substrate ( 102 ) in parts of the first voltage area ( 102 A) and the second voltage area ( 102 B), and the substrate ( 102 ) not protected by the second mask layer ( 106 ) is etched to form a trench (TR) such that the STI structure ( 200 ) is formed within the trench (TR).

11. The method of forming the semiconductor device according to claim 8 , wherein after forming the STI structure ( 200 ), further comprises the steps of:

partially removing the first portion ( 200 A) of the STI structure ( 200 ) in the first voltage area ( 102 A);

forming a second oxide layer (OL 2 ) on the first voltage area ( 102 A) and forming a third oxide layer (OL 3 ) on the second voltage area ( 102 B), wherein the second oxide layer (OL 2 ) grows up and down from the top surface ( 102 T) of the substrate ( 102 ) in the first voltage area ( 102 A), and the third oxide layer (OL 3 ) grows up and down from the top surface ( 102 T) of the substrate ( 102 ) in the second voltage area ( 102 B); and

removing the third oxide layer (OL 3 ) and partially removing the second portion ( 200 B) of the STI structure ( 200 ) located in the second voltage area ( 102 B), such that the top surface (TS) of the STI structure ( 200 ), the top surface (OLT) of the second oxide layer (OL 2 ) and the top surface ( 102 T) of the substrate ( 102 ) in the second voltage area ( 102 B) are substantially coplanar to generate a coplanar surface ( 102 T/TS/OLT).

12. The method of forming the semiconductor device according to claim 11 , wherein a bottom surface of the second oxide layer (OL 2 ) is located below the coplanar surface ( 102 T/TS/OLT).

13. The method of forming the semiconductor device according to claim 11 , wherein after the formation of the STI structure ( 200 ) and prior to the partial removal of the first portion ( 200 A) of the STI structure ( 200 ) in the first voltage area ( 102 A), the second portion ( 200 B) of the STI structure ( 200 ) in the second voltage area ( 102 B) is covered with a third mask layer ( 108 ), and the first portion ( 200 A) of the STI structure ( 200 ) in the first voltage area ( 102 A) is partially removed by wet etching.

14. The method of forming the semiconductor device according to claim 13 , wherein prior to the removal of the third oxide layer (OL 3 ) and the partial removal of the second portion ( 200 B) of the STI structure ( 200 ), the second oxide layer (OL 2 ) and the first portion ( 200 A) of the STI structure ( 200 ) in the first voltage area ( 102 A) is covered with a fourth mask layer ( 110 ), and the removal of the third oxide layer (OL 3 ) and the partial removal of the second portion ( 200 B) of the STI structure ( 200 ) is then performed by wet etching.

15. The method of forming the semiconductor device according to claim 8 , wherein the recess has a recess depth H 1 , and a step height difference H 2 exist between the bottom surface (BS 1 ) of the first portion ( 200 A) of the STI structure ( 200 ) in the first voltage area ( 102 A) and the bottom surface (BS 2 ) of the second portion ( 200 B) of the STI structure ( 200 ) in the second voltage area ( 102 B), wherein H 1 =H 2 .

16. The method of forming the semiconductor device according to claim 8 , wherein an operating voltage of the first voltage area ( 102 A) is from 6V to 8V.

17. The method of forming the semiconductor device according to claim 8 , wherein an operating voltage of the second voltage area ( 102 B) is from 0.9V to 1V.