Systems and methods for managing write voltages in a cross-point memory array
Techniques are provided for managing voltages applied to memory cells in a cross-point array during a write operation (e.g., to transition from a resistive state into a conductive state). The techniques apply to thyristor memory cells and non-thyristor memory cells. Bitlines, connected by a wordline, are preconditioned to a voltage level, by a precondition device, to write data to one or more memory cells at intersections of the bitlines and the wordline. Each bitline is coupled to a high impedance device, a detect device, a precondition device and a clamp device. When a memory cell on a first bitline transitions from a resistive state into a conductive state, it pulls a voltage level of the first-bit line level low. A first clamp device maintains the voltage level at a level to de-bias the first bitline from the wordline, while other memory cells to be written along the wordline remain biased.
1. An apparatus for regulating applied voltage in a cross-point memory array during a write operation, the apparatus comprising:
a first device connected to an electrically conducting line and configured to set a voltage of the electrically conducting line;
a voltage level detect device comprising an input, connected to the electrically conducting line, and an output;
a high impedance device comprising an input connected to the output of the voltage level detect device, and an output connected to the electrically conducting line; and
a clamp device connected to the electrically conducting line.
2. The apparatus of claim 1 , wherein the electrically conducting line is a bitline.
3. The apparatus of claim 1 , wherein the electrically conducting line is a wordline.
4. The apparatus of claim 1 , wherein the clamp device comprises a bipolar junction transistor, wherein at least one of an emitter and a collector of the bipolar junction transistor is connected to a second power supply.
5. The apparatus of claim 1 , wherein the clamp device comprises an NMOS transistor, wherein at least one of a source and a drain of the NMOS transistor is connected to a second power supply.
6. The apparatus of claim 1 , wherein the voltage level detect device comprises an inverter, wherein an input of the inverter is connected to the input of the voltage level detect device and an output of the inverter is connected to the output of the voltage level detect device.
7. The apparatus of claim 1 , wherein the high impedance device comprises:
a high impedance PMOS transistor; and
a shut-off PMOS transistor, connected to the high impedance PMOS transistor and the electrically conducting line, comprising a gate connected to the input of the high impedance device.
8. The apparatus of claim 1 , wherein the first device comprises a PMOS transistor connected to the electrically conducting line.
9. The apparatus of claim 1 , wherein the electrically conducting line is connected to a thyristor memory cell and the first device is connected to a first power supply that provides a first voltage level that is greater than a turn-on voltage of the thryristor memory cell.
10. The apparatus of claim 9 , wherein the clamp device is connected to a second power supply that provides a second voltage level that is less than the first voltage level and higher than a turn-off voltage of the thyristor memory cell.
11. An apparatus for regulating applied voltage in a cross-point memory array during a write operation, the apparatus comprising:
a first device connected to an electrically conducting line and configured to set a voltage of the electrically conducting line;
a voltage level detect device comprising an input connected to the electrically conducting line and configured to generate a shutoff control signal as an output based on detecting that a voltage level of the electrically conducting line falls below a threshold;
a high impedance device comprising an input connected to the output of the voltage level detect device, and an output connected to the electrically conducting line, wherein the high impedance device is configured to disconnect a first power supply from the electrically conducting line based on receiving the shutoff control signal from the voltage level detect device; and
a clamp device connected to the electrically conducting line.
12. The apparatus of claim 11 , wherein the electrically conducting line is a bitline.
13. The apparatus of claim 11 , wherein the electrically conducting line is a wordline.
14. The apparatus of claim 11 , wherein the clamp device comprises a bipolar junction transistor, wherein at least one of an emitter and a collector of the bipolar junction transistor is connected to a second power supply.
15. The apparatus of claim 11 , wherein the clamp device comprises an NMOS transistor, wherein at least one of a source and a drain of the NMOS transistor is connected to a second power supply.
16. The apparatus of claim 11 , wherein the voltage level detect device comprises an inverter, wherein an input of the inverter is connected to the input of the voltage level detect device and an output of the inverter is connected to the output of the voltage level detect device.
17. The apparatus of claim 11 , wherein the high impedance device comprises:
a high impedance PMOS transistor connected to the first power supply; and
a shut-off PMOS transistor, connected to the high impedance PMOS transistor and the electrically conducting line, comprising a gate connected to the input of the high impedance device.
18. The apparatus of claim 11 , wherein the first device comprises a PMOS transistor connected to the electrically conducting line and the first power supply.
19. The apparatus of claim 11 , wherein the electrically conducting line is connected to a thyristor memory cell, and wherein the first power supply provides a first voltage level that is greater than a turn-on voltage of the thryristor memory cell.
20. The apparatus of claim 19 , wherein a second power supply, connected to the clamp device, provides a second voltage level that is less than the first voltage level and higher than a turn-off voltage of the thyristor memory cell.