VERTICAL MEMORY DEVICES

1 . A vertical memory device, comprising:

a substrate;

a plurality of channels on the substrate, the channels extending in a first direction that is vertical to a top surface of the substrate;

a plurality of gate lines stacked on top of each other on the substrate, the gate lines surrounding the channels, the gate lines spaced apart from each other along the first direction; and

a conductive line on the substrate and cutting the gate lines along the first direction, a width of the conductive line being periodically and repeatedly changed.

2 . The vertical memory device of claim 1 , further comprising:

a plurality of conductive lines on the substrate, wherein

the conductive lines include the conductive line,

the conductive lines extend in a second direction parallel to the top surface of the substrate, and

the conductive lines are spaced apart from each other in a third direction that is parallel to the top surface of the substrate and crosses the second direction.

3 . The vertical memory device of claim 2 , wherein

the conductive lines each include first portions and second portions that are alternately repeated, and

a width of the second portions in the third direction is greater than a width of the first portions in the third direction.

4 . The vertical memory device of claim 3 , wherein

the second portions in different conductive lines among the plurality of conductive lines are arranged in a staggered configuration or a zigzag configuration in a plan view.

5 . The vertical memory device of claim 4 , wherein the first portions and the second portions included in the different conductive lines face each other in the third direction.

6 . The vertical memory device of claim 3 , wherein the second portion has a rectangular cross-section in the plan view.

7 . The vertical memory device of claim 3 , wherein the second portions have an elliptical cross-section in the plan view.

8 . The vertical memory device of claim 7 , wherein a boundary area between the first portions and the second portions includes a curved portion.

9 . The vertical memory device of claim 3 , wherein the conductive lines include at least one third portion configured as a pad.

10 . The vertical memory device of claim 9 , wherein a width in the third direction of the third portion is greater than a width in the third direction of the second portion.

11 . The vertical memory device of claim 9 , wherein the third portions included in different conductive lines of the plurality of the conductive lines are staggered along the third direction in a plan view.

12 . The vertical memory device of claim 9 , wherein the third portion and the second portions have different shape in a plan view.

13 . The vertical memory device of claim 3 , further comprising:

an insulation spacer formed along a sidewall of the conductive line.

14 . The vertical memory device of claim 13 , wherein a thickness of a portion of the insulation spacer that contacts the first portions is greater than a thickness of a portion of the insulation spacers that contacts the second portions.

15 . A vertical memory device, comprising:

a substrate;

a plurality of cell blocks on the substrate, a cell block among the plurality of the cell blocks including,

a plurality of channels extending in a first direction vertical to a top surface of the substrate, and

a plurality of gate lines stacked on top of each other on the substrate, the gate lines surrounding the channels, the gate lines being spaced apart from each other along the first direction; and

a conductive line on the substrate, the conductive line including a plurality of embossed patterns, the conductive line extending between two of the cell blocks.

16 . The vertical memory device of claim 15 , wherein

the cell block further includes insulating interlayer patterns,

the insulating interlayer patterns are between the gate lines,

an uppermost insulating interlayer pattern of the insulating interlayer patterns is on an uppermost gate line of the gate lines, and

the conductive line extends in the first direction through the insulating interlayer patterns and the gate lines.

17 . The vertical memory device of claim 16 , wherein

an upper portion of the substrate includes an impurity region,

the conductive line is electrically connected to the impurity region, and the impurity region is a common source line (CSL).

18 - 21 . (canceled)

22 . A vertical memory device, comprising:

a substrate including a cell region, an extension region and a peripheral region;

channels on the cell region of the substrate, the channels extending in a first direction vertical to a top surface of the substrate;

gate lines stacked on top of each other in the first direction on the substrate,

the gate lines surrounding the channels, the gate lines extending in a second direction parallel to the top surface of the substrate over the cell region and the extension region;

a conductive line on the substrate and cutting the gate lines along the first direction,

the conductive line extending in the second direction over the cell region and the extension region,

the conductive line including first portions and second portions that have different widths in a third direction,

the third direction being perpendicular to the second direction and parallel to the top surface of the substrate;

first contacts electrically connected to the gate lines, the first contacts being arranged on the extension region;

first wirings electrically connected to the gate lines via the first contacts,

the first wirings extending from the extension region to the peripheral region; and

a second wiring electrically connected to the conductive line.

23 . The vertical memory device of claim 11 , further comprising:

a second contact that connects the second wiring to the conductive line.

24 . The vertical memory device of claim 23 , wherein the conductive line further includes a third portion that is a pad for the second contact.

25 - 37 . (canceled)