Single poly nonvolatile memory device
A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.
1. A single-poly nonvolatile memory (NVM) cell, comprising:
a semiconductor substrate;
an ion well in the semiconductor substrate;
a select transistor on the ion well, wherein the select transistor comprises a select gate, a select gate oxide layer between the select gate and the semiconductor substrate, a source doping region in the ion well, a first lightly doped drain (LDD) region merged with the source doping region, a commonly-shared doping region spaced apart from the source doping region, and a second LDD region merged with the commonly-shared doping region;
a floating gate transistor serially connected to the select transistor, wherein the floating gate transistor comprises a floating gate, a floating gate oxide layer between the floating gate and the semiconductor substrate, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region spaced apart from the commonly-shared doping region;
a drain-side extension modified region under the spacer and in proximity to the drain doping region;
a first salicide layer on the source doping region; and
a silicide block (SAB) layer covering and being in direct contact with the floating gate.
2. The single-poly NVM cell according to claim 1 , wherein a doping concentration of the drain-side extension modified region is the same as that of the ion well.
3. The single-poly NVM cell according to claim 1 , wherein the drain-side extension modified region has a conductivity type that is different from that of the drain doping region.
4. The single-poly NVM cell according to claim 1 , wherein a doping concentration of the drain-side extension modified region is lower than that of the drain doping region.
5. The single-poly NVM cell according to claim 1 further comprising:
a contact etch stop layer on the SAB layer, wherein the floating gate is isolated from the contact etch stop layer by the SAB layer.
6. The single-poly NVM cell according to claim 5 further comprising:
an inter-layer dielectric (ILD) layer on the contact etch stop layer.
7. The single-poly NVM cell according to claim 1 further comprising a first sidewall spacer provided on each sidewall of the select gate, and a second sidewall spacer provided on each sidewall of the floating gate.
8. The single-poly NVM cell according to claim 7 , wherein the first salicide layer extends to an edge of a bottom of the first sidewall spacer.
9. The single-poly NVM cell according to claim 8 further comprising a second salicide layer on the commonly shared doping region, wherein the second salicide layer is contiguous with an edge of a bottom of the first sidewall spacer, but is kept a predetermined distance from an edge of a bottom of the second sidewall spacer.
10. The single-poly NVM cell according to claim 9 further comprising a third salicide layer on the drain doping region, wherein the third salicide layer is kept a predetermined distance from an edge of a bottom of the second sidewall spacer.
11. The single-poly NVM cell according to claim 10 further comprising a fourth salicide layer on a top surface of the select gate.
12. The single-poly NVM cell according to claim 1 , wherein no silicide layer is formed on a top surface of the floating gate.
13. The single-poly NVM cell according to claim 1 , wherein the SAB layer comprises silicon oxide.
14. The single-poly NVM cell according to claim 7 , wherein the SAB layer covers and is in direct contact with a top surface of the floating gate, surfaces of the second sidewall spacers, only a portion of the commonly shared doping region, and only a portion of the drain doping region.
15. The single-poly NVM cell according to claim 1 , wherein the select transistor and the floating gate transistor are both a PMOS transistor.
16. The single-poly NVM cell according to claim 15 , wherein the ion well is an N well, and wherein the source doping region, the commonly shared doping region, and the drain doping region are P + doping regions.
17. The single-poly NVM cell according to claim 16 , wherein the first LDD region, the second LDD region, and the third LDD region are PLDD regions.