RF switch having reduced signal distortion
An RF switch having an M number of FETs that are stacked in series and coupled between a first end node and a second end node wherein each of the M number of FETs has a gate is disclosed. A resistive network is coupled between a common mode (CM) node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal. Biasing circuitry coupled to the CM node is configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state.
1. An RF switch having a common mode (CM) node, a first end node, and a second end node comprising:
an M number of FETs that are stacked in series and coupled between the first end node and the second end node wherein M is a finite number greater than one and each of the M number of FETs has a gate;
a resistive network coupled between the CM node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal; and
biasing circuitry coupled to the CM node and configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state.
2. The RF switch of claim 1 wherein the M number of FETs comprise:
a first end FET coupled to the first end node and having a first gate;
an M th end FET coupled to the second end node and having a second gate; and
M−2 FETs stacked in series with and in between the first end FET and the M th end FET;
M−1 bias resistors coupled in series between the first gate and the CM node, wherein each of the M−1 bias resistors have a resistance of substantially R;
a first gate resistor coupled between the second gate and the CM node and having a resistance of substantially (M−1)·R; and
M−2 gate resistors wherein each of the M−2 gate resistors is coupled between a gate of one of the M−2 FETs and a connection node between adjacent ones of the M−1 bias resistors, wherein when progressing from the first end node to the second end node successive ones of the M−2 gate resistors has a resistance that increases by R.
3. The RF switch of claim 2 further including a CM mode resistor coupled between the CM node and a control node.
4. The RF switch of claim 3 wherein the biasing circuitry comprises:
a current mirror having a mirror output, a drive input, and a drive output coupled to the control node;
an operational amplifier (op-amp) having a non-inverting input coupled to the control node, an inverting input coupled to the mirror output, and an op-amp output coupled to the drive input; and
a compensation resistor coupled between the inverting input and a first fixed voltage node.
5. The RF switch of claim 4 wherein the current mirror comprises:
a drive FET having the drive input, the drive output, and a drive source coupled to a second fixed voltage node;
a mirror FET having the mirror output, a mirror gate coupled to the op-amp output, and a mirror source coupled to the second fixed voltage node.
6. The RF switch of claim 5 wherein the drive FET and the mirror FET are both n-channel FETs.
7. The RF switch of claim 5 wherein the first fixed voltage node and the second fixed voltage node are at a negative potential with respect to a ground node.
8. The RF switch of claim 3 wherein the biasing circuitry comprises:
a drive FET having a drive drain coupled to the CM node, a drive source coupled to a first fixed voltage node, and a drive gate;
an operational amplifier (op-amp) having a non-inverting input coupled to the control node, an inverting input, and an op-amp output coupled to the drive gate; and
a low-pass filter coupled between the drive drain and the inverting input.
9. The RF switch of claim 8 wherein the drive FET is an n-channel FET.
10. The RF switch of claim 9 wherein the first fixed voltage node is at a negative potential with respect to a ground node.
11. The RF switch of claim 2 further including a speed-up device comprising an M number of p-FETS that are stacked in series and coupled between the first gate and the second gate, and wherein each of the M number of p-FETs is coupled between adjacent gates of the M number of FETs.
12. The RF switch of claim 1 wherein the M number of FETs comprise:
a first end FET coupled to the first end node and having a first gate;
M/2−1 first FETs stacked in series with and in between the first end FET and a middle node;
M/2 first bias resistors coupled in series between the first gate and the CM node, wherein each of the M/2 first bias resistors have a resistance of substantially R; and
M/2−1 first gate resistors wherein each of the M/2−1 first gate resistors is coupled between a gate of one of the M/2−1 first FETs and a connection node between adjacent ones of the M/2 first bias resistors, wherein when progressing from the first end node to the middle node successive ones the M/2−1 first gate resistors has a resistance that increases by R.
13. The RF switch of claim 12 further comprising:
a second end FET coupled to the second end node and having a second gate;
M/2−1 second FETs stacked in series with and in between the second end FET and the middle node;
M/2 second bias resistors coupled in series between the second gate and the CM node, wherein each of the M/2 second bias resistors have a resistance of substantially R; and
M/2−1 second gate resistors wherein each of the M/2−1 second gate resistors is coupled between a gate of one of the M/2−1 second FETs and a connection node between adjacent ones of the M/2 second bias resistors, wherein when progressing from the second end node to the middle node successive ones of the M/2−1 second FETs each one of the M/2−1 second gate resistors has a resistance that increases by R.
14. The RF switch of claim 13 further including a CM mode resistor coupled between the CM node and a control node.
15. The RF switch of claim 14 wherein the biasing circuitry comprises:
a current mirror having a mirror output, a drive input, and a drive output coupled to the control node;
an operational amplifier (op-amp) having a non-inverting input coupled to the control node, an inverting input coupled to the mirror output, and an op-amp output coupled to the drive input; and
a compensation resistor coupled between the inverting input and a first fixed voltage node.
16. The RF switch of claim 15 wherein the current mirror comprises:
a drive FET having the drive input, the drive output, and a drive source coupled to a second fixed voltage node;
a mirror FET having the mirror output, a mirror gate coupled to the op-amp output, and a mirror source coupled to the second fixed voltage node.
17. The RF switch of claim 16 wherein the drive FET and the mirror FET are both n-channel FETs.
18. The RF switch of claim 16 wherein the first fixed voltage node and the second fixed voltage node are at a negative potential with respect to a ground node.
19. The RF switch of claim 14 wherein the biasing circuitry comprises:
a drive FET having a drive drain coupled to the CM node, a drive source coupled to a first fixed voltage node, and a drive gate;
an operational amplifier (op-amp) having a non-inverting input coupled to the control node, an inverting input, and an op-amp output coupled to the drive gate; and
a low-pass filter coupled between the drive drain and the inverting input.
20. The RF switch of claim 19 wherein the drive FET is an n-channel FET.
21. The RF switch of claim 20 wherein the first fixed voltage node is at a negative potential with respect to a ground node.