Vector checksum instruction
View Patent ↗A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.
1. A method of executing a machine instruction in a central processing unit, the method comprising:
obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation;
a first register field to be used to designate a first register, the first register comprising a first operand;
a second register field to be used to designate a second register, the second register comprising a second operand; and
executing the machine instruction, the executing comprising:
adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations;
based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand, wherein the chosen position is bit position zero, the selected position is bit position 31 , and the selected element of the first operand is element one of the first operand; and
placing the first result in the selected element of the first operand, and placing zeros in one or more other elements of the first operand.
2. The method of claim 1 , wherein the first operand comprises four word-sized elements, and wherein the placing comprises placing zeros in elements zero, two and three of the first operand.
3. The method of claim 1 , wherein the plurality of elements of the second operand comprises a plurality of word-sized elements.
4. The method of claim 1 , wherein the machine instruction further comprises a third register field to be used to designate a third register, the third register comprising a third operand, and wherein the executing further comprises adding the first result to a selected element of the third operand to obtain a second result, the adding the first result using an end around carry add operation.
5. The method of claim 4 , wherein the machine instruction further comprises an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register, the second register field is combined with a second portion of the extension field to designate the second register, and the third register field is combined with a third portion of the extension field to designate the third register.
6. The method of claim 1 , wherein the executing further comprises adding the first result to a selected element of a third operand to obtain a second result, the adding the first result using an end around carry add operation, and wherein the placing comprises placing the second result in the selected element of the first operand.
7. The method of claim 6 , wherein the third operand is included in the machine instruction.