Processor load using a bit vector to calculate effective address

1. An apparatus, comprising:

a register configured to store a bit vector, wherein the bit vector includes a plurality of elements that occupy N ordered element positions, wherein N is a positive integer; and

circuitry configured to:

identify a particular element position of the bit vector, wherein a value of a element occupying the particular element position matches a first value;

determine an address value using the particular element position of the bit vector and a base address; and

store a data value in the particular element position of the bit vector based on results of a comparison between a second value and data loaded from a location in a memory specified by the address value.

2. The apparatus of claim 1 , wherein to store the data value, the circuitry is further configured to determine which of the data or the second value is greater.

3. The apparatus of claim 1 , wherein to determine the address value, the circuitry is further configured to determine an address offset based on the particular element position.

4. The apparatus of claim 3 , wherein to determine the address offset, the circuitry is further configured to perform a shift operation on a pointer value corresponding to the particular element position.

5. A method, comprising:

receiving a bit vector;

wherein the bit vector includes a plurality of elements that occupy N ordered element positions, wherein N is a positive integer;

identifying a particular element position of the bit vector, wherein a value of a element occupying the particular element position matches a first value;

determining an address value dependent upon the particular element position of the bit vector and a base address; and

storing a data value in the particular element position of the bit vector based on results of comparing a second value and data loaded from a location in a memory specified by the address value.

6. The method of claim 5 , wherein storing the data value includes determining which of the data or the second value is greater.

7. The method of claim 5 , wherein determining the address value includes determining an address offset based on the particular element position.

8. The method of claim 7 , wherein determining the address offset includes performing a shift operation on a pointer value corresponding to the particular element position.

9. The method of claim 7 , further comprising adding the address offset to the base address to generate the address value.

10. The method of claim 5 , further comprising incrementing a pointer value corresponding to the particular element position in response to determining the address value.

11. A system, comprising:

a memory; and

a processor configured to:

fetch an instruction from the memory;

identify a particular element position of a bit vector in response to a determination that the instruction is a bit vector instruction, wherein the bit vector includes a plurality of elements that occupy N ordered element positions, wherein N is a positive integer, and wherein a value of an element occupying the particular element position matches a first predetermined value;

determine an address value dependent upon the particular element position of the bit vector and a base address; and

store a data value in the particular element position of the bit vector based on results of a comparison between a second value and data loaded from a location in the memory specified by the address value.

12. The system of claim 11 , wherein to store the data value, the processor is further configured to determine which of the data or the second value is greater.

13. The system of claim 11 , wherein to determine the address value, the processor is further configured to determine an address offset based on the particular element position.

14. The system of claim 13 , wherein to determine the address offset, the processor is further configured to perform a shift operation on a pointer value corresponding to the particular element position.