Vertical FET symmetric and asymmetric source/drain formation
A method for forming features of a vertical FET device, starting with a semiconductor substrate that includes fins and a horizontal surface. The fins also have a base, a top, and sidewalls. An etch process is performed to create bottom lateral recesses at the base of the fins. The method continues with growing a bottom source/drain region in the bottom recesses which forms PN junctions, and etching the fins to form top lateral recesses at the top of the fins. The method continues with growing a top source/drain region in the top recesses of the fins, therefore forming PN junctions.
1. A method for forming features of a vertical field-effect transistor (FET), the method comprising:
forming a semiconductor substrate that includes a fin structure, wherein the substrate includes a horizontal surface, and wherein the fin structure including a base, a top, and sidewalls;
etching the fin structure sidewalls to form bottom lateral recesses at the base of the fin structure;
growing a bottom source/drain region in the bottom lateral recesses of the fin structure, therefore forming PN junctions with the fin structure;
etching the fin structure sidewalls to form top lateral recesses at the top of the fin structure; and
growing a top source/drain region in the top lateral recesses of the fin structure, therefore forming PN junctions with the fin structure.
2. The method of claim 1 further comprising depositing a mask on the top and sidewalls of the fin structure and on the horizontal surface of the substrate, and etching away the mask on a lower portion of the sidewalls of the fin structure.
3. The method of claim 1 further comprising depositing a bottom spacer, a high-k gate structure, and a top spacer over the bottom source/drain region.
4. The method of claim 1 , wherein the bottom and top source/drain regions are identical in shape, forming symmetric bottom and top source/drain regions.
5. The method of claim 1 , wherein the bottom and top source/drain regions are different in shape, forming asymmetric bottom and top source/drain regions.
6. The method of claim 1 further comprising an annealing step to push the bottom source/drain region further into the fin, therefore extending the PN junctions.
7. The method of claim 1 further comprising an annealing step to push the top source/drain region further into the fin, therefore extending the PN junctions.
8. The method of claim 1 , wherein the bottom source/drain region is doped.
9. The method of claim 1 , wherein the top source/drain region is doped.
10. The method of claim 1 , wherein the bottom and top source/drain regions are comprised of silicon germanium (SiGe).
11. A semiconductor field-effect transistor (FET) device comprising:
a semiconductor substrate that includes a vertical fin structure;
a bottom lateral recess in the fin structure, the bottom lateral recess containing a bottom source/drain region, therefore forming PN junctions with the fin structure; and
a top lateral recess in the fin structure, the top lateral recess containing a top source/drain region, therefore forming PN junctions with the fin structure.
12. The device of claim 11 , wherein the bottom and top source/drain regions are identical in shape, forming symmetric bottom and top source/drain regions.
13. The device of claim 11 , wherein the bottom and top source/drain regions are different in shape, forming asymmetric bottom and top source/drain regions.
14. The device of claim 11 further comprising a bottom spacer, a high-k gate structure, and a top spacer over the bottom source/drain region.
15. The device of claim 11 further comprising a metal contact layer over the fin structure and top source/drain region.
16. The device of claim 11 , wherein the source/drain regions are annealed to extend the PN junctions by bringing dopants closer to the surface of the recesses.
17. The device of claim 11 , wherein the device can be tuned by changing the shape of the bottom source/drain regions.
18. The device of claim 11 , wherein the device can be tuned by changing the shape of the top source/drain regions.
19. The device of claim 11 , wherein the bottom source/drain region is doped.
20. The device of claim 11 , wherein the top source/drain region is doped.