IP Library Granted Patent US 9,754,916
Granted Patent B2
US 9,754,916 · App. 15/297,948 · Granted Sep 5, 2017

Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

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Quick Facts
Patent No.
US 9,754,916
App. No.
15/297,948
Granted
Sep 5, 2017
Kind
B2
Abstract

Embodiments of the present disclosure provide a semiconductor device, a semiconductor package, and a method for manufacturing a semiconductor device. The semiconductor device comprises: a semiconductor die; an electrical isolation layer formed on a surface of the semiconductor die; a substrate; and a non-conductive adhesive layer disposed between the electrical isolation layer and the substrate, so as to adhere the electrical isolation layer to the substrate.

Claims (58)

1. A method for manufacturing a semiconductor device, comprising:

forming an electrical isolation layer on a surface of a semiconductor wafer, the electrical isolation layer abutting the semiconductor wafer;

attaching an adhesive layer to the electrical isolation layer;

dicing the semiconductor wafer and the electrical isolation layer to form a monolithic structure, the monolithic structure comprising a semiconductor die; and

adhering the monolithic structure to a substrate via the adhesive layer, wherein the adhesive layer is disposed between the electrical isolation layer and the substrate, the electrical isolation layer being harder than the adhesive layer,

wherein the attaching of the adhesive layer occurs in time sequence after the dicing of the wafer, and the adhesive layer is attached to the electrical isolation layer when it is in the form of the monolithic structure of the semiconductor die.

2. The method according to claim 1 wherein the adhesive layer is a die attach film.

3. The method of claim 1 wherein the adhesive layer is attached to the die before the die is attached to substrate.

4. A method for manufacturing a semiconductor device, comprising:

forming an electrical isolation layer on a surface of a semiconductor wafer, the electrical isolation layer abutting the semiconductor wafer;

attaching an adhesive layer to the electrical isolation layer;

dicing the semiconductor wafer and the electrical isolation layer to form a monolithic structure, the monolithic structure comprising a semiconductor die; and

adhering the monolithic structure to a substrate via the adhesive layer, wherein the adhesive layer is disposed between the electrical isolation layer and the substrate, the electrical isolation layer being harder than the adhesive layer,

wherein the attaching of the adhesive layer occurs in time sequence before the dicing of the wafer and the dicing of the semiconductor wafer includes dicing the semiconductor wafer, the electrical isolation layer, and the adhesive layer in a single step to form the monolithic structure, the monolithic structure comprising the semiconductor die.

5. The method according to claim 4 wherein the electrical isolation layer has a Rockwell hardness E scale value of at least 52.

6. A method for manufacturing a semiconductor device, comprising:

forming an electrical isolation layer on a surface of a semiconductor wafer, the electrical isolation layer abutting the semiconductor wafer;

attaching an adhesive layer to the electrical isolation layer;

dicing the semiconductor wafer and the electrical isolation layer to form a monolithic structure, the monolithic structure comprising a semiconductor die;

adhering the monolithic structure to a substrate via the adhesive layer, wherein the adhesive layer is disposed between the electrical isolation layer and the substrate, the electrical isolation layer being harder than the adhesive layer; and

encapsulating the monolithic structure and the substrate with a molding compound to form a package.

7. The method according to claim 6 , further comprising:

adhering a further semiconductor die to the substrate using a conductive adhesive layer; and

encapsulating the monolithic structure, the further semiconductor die, and the substrate with a molding compound to form a package.

8. A method for manufacturing a semiconductor device, comprising:

forming an electrical isolation layer on a surface of a semiconductor wafer, the electrical isolation layer abutting the semiconductor wafer;

dicing the semiconductor wafer and the electrical isolation layer to form a monolithic structure, the monolithic structure comprising a semiconductor die; and

adhering the monolithic structure to a substrate using an adhesive glue, wherein the adhesive glue is disposed between the electrical isolation layer and the substrate, the electrical isolation layer being harder than the adhesive glue,

wherein the adhering of the monolithic structure to the substrate occurs in time sequence after the dicing of the semiconductor wafer, and the adhesive glue is attached to the electrical isolation layer when it is in the form of the monolithic structure of the semiconductor wafer.

9. The method according to claim 8 wherein the adhesive glue is a die attach film.

10. The method of claim 8 wherein the adhesive glue is attached to the wafer before the wafer is attached to substrate.

11. The method according to claim 8 wherein the electrical isolation layer has a Rockwell hardness E scale value of at least 52.

12. A method for manufacturing a semiconductor device, comprising:

forming an electrical isolation layer on a surface of a semiconductor wafer, the electrical isolation layer abutting the semiconductor wafer;

dicing the semiconductor wafer and the electrical isolation layer to form a monolithic structure, the monolithic structure comprising a semiconductor die; and

adhering the monolithic structure to a substrate using an adhesive glue, wherein the adhesive glue is disposed between the electrical isolation layer and the substrate, the electrical isolation layer being harder than the adhesive glue,

wherein the adhering of the monolithic structure to the substrate occurs in time sequence before the dicing of the wafer and the dicing of the semiconductor wafer includes dicing the semiconductor wafer, the electrical isolation layer, and the adhesive glue in a single step to form the monolithic structure, the monolithic structure comprising the semiconductor die.

13. A method for manufacturing a semiconductor device, comprising:

forming an electrical isolation layer on a surface of a semiconductor wafer, the electrical isolation layer abutting the semiconductor wafer;

dicing the semiconductor wafer and the electrical isolation layer to form a monolithic structure, the monolithic structure comprising a semiconductor die;

adhering the monolithic structure to a substrate using an adhesive glue, wherein the adhesive glue is disclosed between the electrical isolation layer and the substrate, the electrical isolation layer being harder than the adhesive glue; and

encapsulating the monolithic structure and the substrate with a molding compound to form a package.

14. The method according to claim 13 , further comprising:

adhering a further semiconductor die to the substrate using a conductive adhesive layer; and

encapsulating the monolithic structure, the further semiconductor die, and the substrate with a molding compound to form a package.

15. A method, comprising:

forming an electrical isolation layer on a surface of a semiconductor wafer, the electrical isolation layer abutting the semiconductor die and having a Rockwell hardness E scale value of at least 52;

attaching an adhesive layer to the electrical isolation layer;

dicing the semiconductor wafer, the electrical isolation layer, and the adhesive layer to form a monolithic structure, the monolithic structure comprising a semiconductor die; and

adhering the monolithic structure to a substrate via the adhesive layer, wherein the adhesive layer is disposed between the electrical isolation layer and the substrate, the electrical isolation layer being harder than the adhesive layer.

16. The method according to claim 15 wherein the semiconductor die comprises a bonding pad, the bonding pad being disposed at another surface of the semiconductor wafer opposite to the surface, and wherein the method further comprises:

providing a lead; and

connecting the lead to the bonding pad via a bonding wire, the connecting of the lead to the bonding pad via the bonding wire being performed using a thermal ultrasonic technique.

17. The method according to claim 15 , further comprising:

encapsulating the monolithic structure and the substrate with a molding compound to form a package.

18. The method according to claim 15 , further comprising:

adhering a further semiconductor die to the substrate using a conductive adhesive layer; and

encapsulating the monolithic structure, the further semiconductor die, and the substrate with a molding compound to form a package.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068433/0970 →