IP Library Granted Patent US 10,275,330
Granted Patent B2
US 10,275,330 · App. 15/298,291 · Granted Apr 30, 2019

Computer readable non-transitory recording medium storing pseudo failure generation program, generation method, and generation apparatus

Inventor: Hirotsugu Hirano (Kawasaki, JP)
Assignee: FUJITSU LIMITED
G06F11/261G06F11/2236G06F11/263
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Quick Facts
Patent No.
US 10,275,330
App. No.
15/298,291
Granted
Apr 30, 2019
Kind
B2
Abstract

The information processing apparatus includes a processor and components connected to the processor. In this processor, a failure occurring in any one of the processor and the components connected to the processor itself is recorded in a system space accessible in a system management mode, and an interrupt handler is notified of the occurrence of the failure by an interrupt. The program causes a management computer managing the information processing apparatus to execute shifting the processor to the system management mode, setting information indicating a pseudo failure in the system space, shifting the processor to a non system management mode from the system management mode after setting, and causing the processor to generate the interrupt corresponding to the pseudo failure.

Claims (17)

1. A computer readable non-transitory recording medium having stored therein a program for generating a pseudo failure in an information processing apparatus including a processor and components and configured to record an occurrence of failure in any one of the processor and the components connected to the processor in a system space accessible in a system management mode and to notify the occurrence of the failure to an interrupt handler by an interrupt, the program causing a management computer configured to manage the information processing apparatus to execute:

shifting the processor to the system management mode;

setting information indicating a pseudo failure in the system space, the information including elements for the interrupt handler to specify which component the pseudo failure exists in and what kind of the pseudo failure occurs;

shifting the processor to a non system management mode from the system management mode after the setting; and

causing the processor to generate the interrupt corresponding to the pseudo failure.

2. The program according to claim 1 , further causing the management computer to execute acquiring failure information output by the interrupt handler started up by the interrupt.

3. The program according to claim 1 , further causing the management computer to execute accepting a command designating a pseudo failure generating location to generate the pseudo failure from an external device connected to the management computer, and notifying the external device of failure information.

4. A pseudo failure generation method for generating a pseudo failure in an information processing apparatus including a processor and components and configured to record an occurrence of failure in any one of the processor and the components connected to the processor in a system space accessible in a system management mode and to notify the occurrence of the failure to an interrupt handler by an interrupt, the pseudo failure generation method executed by a management computer managing the information processing apparatus, comprising:

shifting the processor to the system management mode;

setting information indicating a pseudo failure in the system space, the information including elements for the interrupt handler to specify which component the pseudo failure exists in and what kind of the pseudo failure occurs;

shifting the processor to a non system management mode from the system management mode after the setting; and

causing the processor to generate the interrupt corresponding to the pseudo failure.

5. A pseudo failure generation apparatus in an information processing apparatus including a processor and components and configured to record an occurrence of failure in any one of the processor and the components connected to the processor in a system space accessible in a system management mode and to notify the occurrence of the failure to an interrupt handler by an interrupt, the pseudo failure generation apparatus including another processor configured to execute a process comprising:

shifting the processor to the system management mode;

setting information indicating a pseudo failure in the system space, the information including elements for the interrupt handler to specify which component the pseudo failure exists in and what kind of the pseudo failure occurs;

shifting the processor to a non system management mode from the system management mode after the setting; and

causing the processor to generate the interrupt corresponding to the pseudo failure.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVER SHEET BY REMOVING PATENT NUMBER 10586039 PREVIOUSLY RECORDED ON REEL 69272 FRAME 546. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2025
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 070764/0091 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 069272/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2016
From: HIRANO, HIROTSUGU
To: FUJITSU LIMITED
Reel/Frame 040424/0203 →
Priority Claims (1)
JP 2015-218286 · Nov 6, 2015 · national
Continuity (1)
Related Publication 20170132102A1 · May 11, 2017
Cited By (1)
US 12,430,203