Method and system for error check and scrub error data collection and reporting for a memory device
A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.
1. A controller for error check and scrub (ECS) error data collection and reporting for a memory device, comprising:
circuitry configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data, wherein the circuitry is further configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold; and
a buffer configured to store the ECS error data,
wherein the controller is a device separate from a processor configured to run the BIOS.
2. The controller of claim 1 , wherein the circuitry is configured to read the ECS error data from the memory device periodically.
3. The controller of claim 2 , wherein the ECS error data includes the total number of ECS errors on the memory device during a predetermined period for ECS operation.
4. The controller of claim 2 , wherein the ECS error data includes a highest number of ECS errors per memory row and a corresponding memory address during a predetermined period for ECS operation.
5. The controller of claim 1 , wherein the controller is a baseboard management controller.
6. The controller of claim 1 , wherein the controller is a memory micro controller.
7. The controller of claim 1 , wherein the memory device is a Double Data Rate (DDR) 5 memory device.
8. A system, comprising:
a memory device including an array of memory cells, circuitry configured to perform error check and scrub (ECS) on the array of memory cells, and registers for storing ECS error data;
the controller of claim 1 ; and
a processor configured to obtain the ECS error data and perform an action to recover a failed memory in the array of memory cells in response to an interrupt by the controller.
9. The system of claim 8 , wherein the processor is configured to read the ECS error data from the controller upon reception of the interrupt.
10. The system of claim 8 , wherein the processor is configured to perform post-package repair (PPR) or adaptive double DRAM device correction (ADDDC) after obtaining the ECS error data to recover a failed memory.
11. The system of claim 8 , wherein the controller is a baseboard management controller (BMC) or a memory micro-controller (MMC).
12. The system of claim 8 , wherein the processor is configured to report an error log to an operating system.
13. A method for error check and scrub (ECS) error data collection and reporting for a memory device, comprising:
reading, by a controller, ECS error data from a register of a memory device;
calculating, by the controller, an ECS error increase rate based on the ECS error data; and
informing, by the controller, basic input/output system (BIOS) if an ECS error number reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold, wherein the controller is a device separate from a processor configured to run the BIOS.
14. The method of claim 13 , further comprising saving the ECS error data in a buffer.
15. The method of claim 13 , wherein the ECS error data is read from the memory device periodically.
16. The method of claim 13 , wherein the ECS error data includes a total number of ECS errors on the memory device during a predetermined period for ECS operation.
17. The method of claim 13 , wherein the ECS error data includes a highest number of ECS errors per memory row and a corresponding memory address during a predetermined period for ECS operation.
18. The method of claim 13 , wherein the method is implemented by a baseboard management controller or a memory micro controller.
19. The method of claim 13 , wherein the memory device is a Double Data Rate (DDR) 5 memory device.