Tunable barrier transistors for high power electronics

1. A tunable barrier transistor, comprising:

an inorganic semiconducting layer;

a source electrode comprising a porous nano-carbon film disposed on a portion of a first side of the inorganic semiconducting layer, the porous nano-carbon film forming a source-channel interface with the inorganic semiconducting layer that includes open regions in the porous nano-carbon film;

a gate dielectric layer disposed on the porous nano-carbon film of the source electrode; and

a gate electrode disposed on the gate dielectric layer over at least a portion of the porous nano-carbon film, where a gate field produced by the gate electrode modulates a barrier height at the source-channel interface and modulates a barrier width based, at least in part on, modulating an accumulation of carriers in a semiconductor of the inorganic semiconducting layer in a vicinity of the porous nano-carbon film.

2. The tunable barrier transistor of claim 1 , wherein the inorganic semiconducting layer comprises a crystalline semiconductor.

3. The tunable barrier transistor of claim 2 , wherein the crystalline semiconductor is a single crystal semiconductor.

4. The tunable barrier transistor of claim 2 , wherein the inorganic semiconducting layer comprises silicon (Si), gallium nitride (GaN), silicon carbide (SiC), aluminum nitride (AlN), or diamond.

5. The tunable barrier transistor of claim 1 , wherein the porous nano-carbon film comprises a dilute network of carbon nanotubes.

6. The tunable barrier transistor of claim 5 , wherein the dilute network of carbon nanotubes has a nanotube surface density in a range of 0.05 μg/cm 2 to 1.0 μg/cm 2 by mass.

7. The tunable barrier transistor of claim 1 , wherein the porous nano-carbon film comprises a sheet of graphene with perforations.

8. The tunable barrier transistor of claim 1 , wherein the gate dielectric layer comprises a high-k dielectric.

9. The tunable barrier transistor of claim 8 , wherein a thickness of the gate dielectric layer is 100 nm or less.

10. The tunable barrier transistor of claim 9 , wherein the gate dielectric layer exhibits dielectric breakdown at greater than 25 Volts.

11. The tunable barrier transistor of claim 1 , further comprising:

a drain electrode comprising a nano-carbon film disposed on another portion of the first side of the inorganic semiconducting layer, the drain electrode separated from the source electrode by a distance, the nano-carbon film of the drain electrode separated from the porous nano-carbon film by a distance, wherein:

the gate dielectric layer is further disposed on the nano-carbon film of the drain electrode and at least a portion of a channel between the source electrode and the drain electrode; and

the gate electrode is further disposed on the gate dielectric layer over at least a portion of the nano-carbon film of the drain electrode that is disposed on the other portion of the first side of the inorganic semiconducting layer.

12. The tunable barrier transistor of claim 11 , wherein the nano-carbon film of the drain electrode comprises a dilute network of carbon nanotubes.

13. The tunable barrier transistor of claim 11 , wherein the nano-carbon film of the drain electrode comprises a sheet of graphene.

14. The tunable barrier transistor of claim 11 , further comprising:

a second dielectric layer disposed on a portion of the first side of the inorganic semiconducting layer; and

a drain contact of the drain electrode disposed on the second dielectric layer, wherein the nano-carbon film of the drain electrode is coupled to the drain contact.

15. The tunable barrier transistor of claim 14 , wherein the gate dielectric layer is further disposed on the drain contact.

16. The tunable barrier transistor of claim 11 , further comprising a back gate electrode disposed on the second side of the inorganic semiconducting layer opposite the first side.

17. The tunable barrier transistor of claim 1 , wherein modulation of the barrier width is based upon modulation of a density of carriers in the porous nano-carbon film and modulation of the barrier width at the source-channel interface by modulating the accumulation of carriers in the semiconductor in the vicinity of the porous nano-carbon film.

18. A tunable barrier transistor, comprising:

an inorganic semiconducting layer having a first side and a second side opposite the first side;

a source electrode comprising a porous nano-carbon film disposed on a portion of the first side of the inorganic semiconducting layer, the porous nano-carbon film forming a source-channel interface with the inorganic semiconducting layer that includes open regions in the porous nano-carbon film;

a gate dielectric layer disposed on the porous nano-carbon film of the source electrode;

a gate electrode disposed on the gate dielectric layer over at least a portion of the porous nano-carbon film, where a gate field produced by the gate electrode modulates a barrier height at the source-channel interface and modulates a barrier width at the source-channel interface based, at least in part on, modulating an accumulation of carriers in a semiconductor of the inorganic semiconductor layer in a vinicity of the porous nano-carbon film;

a second dielectric layer disposed on a portion of the first side of the inorganic semiconducting layer, wherein a portion of the porous nano-carbon film is disposed on the second dielectric layer; and

a source contact of the source electrode disposed on the second dielectric layer, wherein the porous nano-carbon film is coupled to the source contact.

19. The tunable barrier transistor of claim 18 , wherein the gate dielectric layer is further disposed on the source contact.