IP Library Granted Patent US 10,176,043
Granted Patent B2
US 10,176,043 · App. 15/314,902 · Granted Jan 8, 2019

Memory controller

Inventors: Gregg B. Lesartre (Fort Collins, CO); Chris Michael Brueggen (Allen, TX); Lidia Warnes (Roseville, CA)
Assignee: Hewlett Packard Enterprise Development LP
G06F11/1076G06F3/064G06F3/0604G06F3/0619G06F3/0659G06F3/0673G06F11/0727G06F11/0793G06F11/106G06F11/2094G06F2201/81
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Quick Facts
Patent No.
US 10,176,043
App. No.
15/314,902
Granted
Jan 8, 2019
Kind
B2
Abstract

Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.

Claims (35)

1. An apparatus comprising:

a data storage device; and

a memory controller coupled to the data storage device, the memory controller to:

perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device;

determine, during the memory scrubbing operation, whether the corrective action is successful; and

in response to a determination that the corrective action is a failed corrective action, fix a hardware failure of the data storage device by performing another action different than the failed corrective action, based on a type of the hardware failure, wherein the type includes a single data block failure and a multiple data block failure.

2. The apparatus of claim 1 , wherein the memory controller is to perform the memory scrubbing operation independent of an interrupt.

3. The apparatus of claim 1 , wherein when the type is the single data block failure, the memory controller is to re-encode the data block using an encoding mechanism, the encoding mechanism is different from a previous encoding mechanism used to encode the data block prior to the memory scrubbing operation.

4. The apparatus of claim 1 , wherein when the type is the single data block failure, the memory controller is to map the data block to a spare location of the data storage device.

5. The apparatus of claim 1 , wherein when the type is the multiple data block failure, the memory controller is to identify signature information of a memory component of the data storage device where the hardware failure is identified, wherein the signature information is used to determine how to correct the error.

6. The apparatus of claim 1 , wherein the data storage device is implemented using a memristor device.

7. The apparatus of claim 1 , wherein the corrective action uses an error-correcting code to correct the error.

8. A method comprising:

inspecting, via a memory controller, a first data block stored in a data storage device for error during a memory scrubbing operation;

in response to identifying an error associated with the first data block, performing a corrective action to correct the error via the memory controller;

determining whether the corrective action is successful during the memory scrubbing operation;

in response to a determination that the corrective action is a failed corrective action, inspecting a second data block stored in the data storage device to determine a type of a hardware failure of the data storage device; and

fixing the hardware failure based on the type and based on a severity measure of the hardware failure.

9. The method of claim 8 , wherein inspecting the second data block to determine the type of the failure includes:

in response to identifying a second error associated with the second data block, comparing a first data grouping of the error to a second data grouping of the second error;

when there is a common data grouping between the first data grouping and the second data grouping, determining the type of the hardware failure as a multiple data block failure; and

when there is no common data grouping between the first data grouping and the second data grouping, determining the type of the hardware failure as a single data block failure.

10. The method of claim 7 , wherein when the severity measure of the hardware failure does not exceed a threshold, applying an error-correcting code to the first data block each time the first data block is outputted via the memory controller.

11. The method of claim 8 , wherein when the severity measure of the hardware failure exceeds a threshold and the type is a single data block failure, re-encoding the first data block using an encoding mechanism, the encoding mechanism is different from a previous encoding mechanism used to encode the first data block prior to the memory scrubbing operation.

12. The method of claim 8 , wherein when the type is a multiple data block failure, identifying signature information of a memory component of the data storage device where the hardware failure is identified, wherein the signature information is used to determine how to correct the error.

13. A non-transitory computer-readable storage medium comprising instructions when executed cause a memory controller to:

inspect a first data block stored in a data storage device for error during a memory scrubbing operation;

in response to identifying a first error associated with the first data block, perform a corrective action to correct the first error;

in response to determining that the corrective action is a failed corrective action, inspect a second data block stored in the data storage device for error;

in response to identifying a second error associated with the second data block, compare the second error to the first error to determine a type of a hardware failure of the data storage device, wherein the type includes a single data block failure and a multiple data block failure;

when the type is the multiple data block failure, apply a first repair mechanism to fix the hardware failure; and

when the type is the single data block failure, apply a second repair mechanism to fix the hardware failure.

14. The computer-readable storage medium of claim 13 , wherein the first repair mechanism corresponds to identifying signature information of a memory component of the data storage device where the hardware failure is identified, and wherein the signature information is used to determine how to correct the first error.

15. The computer-readable storage medium of claim 13 , wherein the second repair mechanism corresponds to mapping the first data block to a spare location of the data storage device.

16. The computer-readable storage medium of claim 13 , wherein the second repair mechanism corresponds to encoding the first data block using an encoding mechanism, the encoding mechanism is different from a previous encoding mechanism used to encode the first data block prior to the memory scrubbing operation.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2017
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 041315/0182 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2016
From: LESARTRE, GREGG B; BRUEGGEN, CHRIS MICHAEL; WARNES, LIDIA
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 040638/0130 →
Continuity (1)
Related Publication 20170199785A1 · Jul 13, 2017