IP Library Granted Patent US 10,516,522
Granted Patent B2
US 10,516,522 · App. 15/316,714 · Granted Dec 24, 2019

Receiver, transmitter, and communication system

Inventor: Hiroo Takahashi (Kanagawa, JP)
Assignee: Sony Corporation
H04L7/0041G06F1/12G06F13/42G06F13/4291H03K5/159H04L1/0067H03K2005/00019
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Quick Facts
Patent No.
US 10,516,522
App. No.
15/316,714
Granted
Dec 24, 2019
Kind
B2
Abstract

A receiver includes a first receiving circuit that receives a first data including a first symbol transmitted using three signals over a first data lane, the first data lane including three signal lines respectively corresponding to the three signals. The first receiving circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals.

Claims (74)

1. A receiver comprising:

a first receiving circuit configured to receive a first data including a first symbol transmitted using three signals over a first data lane, the first data lane including three signal lines respectively corresponding to the three signals,

wherein the first receiving circuit includes a first delay circuit, a second delay circuit, and a third delay circuit, and

wherein the first receiving circuit includes:

a first amplifier configured to receive a first signal and a second signal of the three signals, and to output a first amplified signal to the first delay circuit,

a second amplifier configured to receive the second signal and a third signal of the three signals, and to output a second amplified signal to the second delay circuit, and

a third amplifier configured to receive the first signal and the third signal of the three signals, and to output a third amplified signal to the third delay circuit.

2. The receiver according to claim 1 , wherein

the first receiving circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals, and

the delay adjustment circuit includes a pattern detection section configured to detect a relative delay amount of at least one of the three signals by using a synchronization code included in the first data.

3. The receiver according to claim 1 , wherein

the first receiving circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals, and

the delay adjustment circuit includes a control section configured to adjust a delay amount of the first delay circuit using a first delay control signal, to adjust a delay amount of the second delay circuit using a second delay control signal, and to adjust a delay amount of the third delay circuit using a third delay control signal.

4. The receiver according to claim 1 , wherein

the first receiving circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals, and

the receiver further comprises a redundant receiving section configured to receive the first data over the first data lane, generate a first delay amount information, and output the first delay amount information to the delay adjustment circuit.

5. The receiver according to claim 1 , wherein the first receiving circuit, in a calibration mode, is configured to:

receive the first data including a delay amount data from a transmitter;

perform a pattern detection to acquire the delay amount data from the first data; and

determine a relative delay amount of at least one of the three signals.

6. The receiver according to claim 5 , wherein the first receiving circuit, in the calibration mode, is further configured to transmit the relative delay amount of at least one of the three signals to the transmitter.

7. The receiver according to claim 1 , further comprising:

a second receiving circuit configured to receive a second data including

a second symbol transmitted using three signals over a second data lane, the second data lane including three signal lines respectively corresponding to the three signals; and

a third receiving circuit configured to receive a third data including a third symbol transmitted using three signals over a third data lane, the third data lane including three signal lines respectively corresponding to the three signals.

8. A transmitter comprising:

a first transmitting circuit configured to transmit a first data including a first symbol transmitted using three signals over a first data lane, the first data lane including three signal lines respectively corresponding to the three signals,

wherein the first transmitting circuit includes a first delay circuit, a second delay circuit, and a third delay circuit, and

wherein the first transmitting circuit includes:

a first amplifier configured to receive a first signal and a second signal of the three signals, and to output a first amplified signal to the first delay circuit,

a second amplifier configured to receive the second signal and a third signal of the three signals, and to output a second amplified signal to the second delay circuit, and

a third amplifier configured to receive the first signal and the third signal of the three signals, and to output a third amplified signal to the third delay circuit.

9. The transmitter according to claim 8 , wherein the first transmitting circuit further includes a control section configured to control a delay amount of at least one of the first delay circuit, the second delay circuit, and the third delay circuit.

10. The transmitter according to claim 9 , wherein

the first transmitting circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals, and

the control section is configured to receive a control signal from the delay adjustment circuit.

11. The transmitter according to claim 8 , wherein the first transmitting circuit, in a calibration mode, is configured to:

set respective delay amounts of the first delay circuit, the second delay circuit, and the third delay circuit to minimum values;

transmit the first data including a delay amount data to a receiver;

receive the delay amount data from the receiver; and

set the respective delay amounts of the first delay circuit, the second delay circuit, and the third delay circuit to corrected values based on the delay amount.

12. The transmitter according to claim 8 , wherein

the first transmitting circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals, and

the delay adjustment circuit is configured to adjust the delay amount in response to a delay amount information signal received from an origin external to the transmitter.

13. The transmitter according to claim 8 , further comprising:

a second transmitting circuit configured to transmit a second data including a second symbol transmitted using three signals over a second data lane, the second data lane including three signal lines respectively corresponding to the three signals; and

a third transmitting circuit configured to transmit a third data including a third symbol transmitted using three signals over a third data lane, the third data lane including three signal lines respectively corresponding to the three signals.

14. An imaging system comprising:

a CMOS image sensor; and

the transmitter according to claim 8 .

15. A mobile communication device comprising:

a wireless communication circuit; and

the transmitter according to claim 8 .

16. A communication system comprising:

a transmitter including a first transmitting circuit configured to transmit a first data including a first symbol transmitted using three signals over a first data lane, the first data lane including three signal lines respectively corresponding to the three signals; and

a receiver including a first receiving circuit configured to receive the first data over the first data lane

wherein the first transmitting circuit and/or the first receiving circuit respectively includes a first delay circuit, a second delay circuit, and a third delay circuit, and

wherein the first transmitting circuit and/or the first receiving circuit respectively includes:

a first amplifier configured to receive a first signal and a second signal of the three signals, and to output a first amplified signal to the first delay circuit,

a second amplifier configured to receive the second signal and a third signal of the three signals, and to output a second amplified signal to the second delay circuit, and

a third amplifier configured to receive the first signal and the third signal of the three signals, and to output a third amplified signal to the third delay circuit.

17. The communication system according to claim 16 , wherein the receiver includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals.

18. The communication system according to claim 16 , wherein the transmitter includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals.

19. The communication system according to claim 16 , wherein the receiver includes a first delay adjustment section configured to adjust a delay amount of at least one of the three signals, and the transmitter includes a second delay adjustment section configured to adjust the delay amount of at least one of the three signals.

20. The communication system according to claim 16 , wherein, in a calibration mode:

the transmitter is configured to:

set respective delay amounts of the first delay circuit, the second delay circuit, and the third delay circuit to minimum values,

transmit the first data including a delay amount data to the receiver, receive a relative delay amount from the receiver; and

set the respective delay amounts of the first delay circuit, the second delay circuit, and the third delay circuit to corrected values based on the delay amount; and

the receiver is configured to:

receive the first data from the transmitter,

perform a pattern detection to acquire the delay amount data from the first data,

determine a relative delay amount of at least one of the three signals, and

transmit the relative delay amount of at least one of the three signals to the transmitter.

Assignments (2)
CHANGE OF NAME Recorded Nov 8, 2021
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 058053/0857 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: TAKAHASHI, HIROO
To: SONY CORPORATION
Reel/Frame 040832/0171 →
Priority Claims (1)
JP 2014-139812 · Jul 7, 2014 · national
Continuity (1)
Related Publication 20170195111A1 · Jul 6, 2017