IP Library › Granted Patent US 10,249,643
Granted Patent B2
US 10,249,643 · App. 15/318,792 · Granted Apr 2, 2019

Hard copied semiconductor device having a resistance-variable non-volatile element

Inventor: Munehiro Tada (Tokyo, JP)
Assignee: NEC CORPORATION
H01L27/11807G06F17/5068H01L27/101H01L27/24H01L27/2436H01L27/2463H01L45/08H01L45/1206H01L2027/11838H01L2027/11875
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Quick Facts
Patent No.
US 10,249,643
App. No.
15/318,792
Granted
Apr 2, 2019
Kind
B2
Abstract

Provided are a semiconductor device and a method of manufacturing the semiconductor device which enable a hard copy of a reconfigurable circuit, which employs a resistance variable element, to be formed at low cost. The method of manufacturing a semiconductor device is for manufacturing a hard copy from a reconfigurable circuit chip that employs a resistance-variable non-volatile element formed inside a multi-layered wiring layer on a semiconductor substrate, wherein the hard copy is manufactured by using a semiconductor substrate base that is the same as that of the semiconductor substrate for forming the reconfigurable circuit chip.

Claims (19)

1. A semiconductor device hard-copied so as to have a same logical operation function as a reconfigurable circuit chip, comprising a resistance-variable non-volatile element formed inside a multi-layered wiring layer on a semiconductor substrate, the resistance-variable non-volatile element having an arbitrary logical operation function being programmed, wherein a lower wiring and an upper wiring planarly overlapping with each other are short-circuited at a portion where the resistance-variable non-volatile element of the reconfigurable circuit chip is programmed to a low-resistance state, and a lower wiring and an upper wiring planarly overlapping with each other are electrically insulated at a portion where the resistance-variable non-volatile element of the reconfigurable circuit chip is programmed to a high-resistance state.

2. The semiconductor device according to claim 1 , wherein

the reconfigurable circuit chip includes a logic block and a switch block, and

the resistance-variable non-volatile element is used for the both blocks.

3. The semiconductor device according to claim 2 , wherein

logic cells including the switch block and the logic block are laid in a shape of tiles.

4. The semiconductor device according to claim 1 , wherein

the switch block includes a crossbar switch.

5. The semiconductor device according to claim 1 , wherein

at least one via plug is formed at the portion programmed to the low-resistance state.

6. A method of manufacturing the semiconductor device according to claim 1 , wherein

a position of the resistance-variable non-volatile element programmed to a low-resistance state during mapping of a reconfigurable circuit is specified, and a layout at a time of hard copy is formed by forming at least one via plug in the multi-layered wiring layer at the position of the low-resistance state element.

7. The method of manufacturing the semiconductor device, according to claim 6 , wherein

the hard copy is manufactured by changing only a single mask in a multi-layered wiring process.

8. The method of manufacturing the semiconductor device, according to claim 6 , wherein

a hard copy is manufactured by using a semiconductor substrate base being same as that of a semiconductor substrate forming the reconfigurable circuit chip.

9. The method of manufacturing the semiconductor device, according to claim 6 , wherein

the resistance-variable non-volatile element includes a wiring serving as a lower electrode, a resistance variable layer, and an upper electrode, and is configured such that the resistance variable layer is connected with the wiring serving as a lower electrode through an opening part of an insulating barrier film provided on the wiring serving as a lower electrode and the upper electrode is connected with an upper wiring through a contact plug, and,

at a time of manufacturing a hard copy, a process of manufacturing the resistance-variable non-volatile element is eliminated and the hard copy is manufactured by changing a mask for forming a via plug for connecting the upper electrode with the upper wiring.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2021
From: NEC CORPORATION
To: NANOBRIDGE SEMICONDUCTOR, INC.
Reel/Frame 054913/0386 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: TADA, MUNEHIRO
To: NEC CORPORATION
Reel/Frame 040734/0698 →
Priority Claims (1)
JP 2014-130223 · Jun 25, 2014 · national
Continuity (1)
Related Publication 20170141125A1 · May 18, 2017