Junction field effect transistor and manufacturing method therefor

1. A junction field effect transistor, comprising:

a substrate;

a buried layer formed in the substrate;

a first well region and a second well region formed on the buried layer;

a source lead-out region, a drain lead-out region, and a first gate lead-out region which are formed in the first well region; and

a second gate lead-out region formed in the second well region;

wherein the substrate has a second doping type, the buried layer comprises a second doping type buried layer, the first well region has a first doping type, the second well region has the second doping type, the first gate lead-out region and the second gate lead-out region have the second doping type, the source lead-out region and the drain lead-out region have the first doping type, the first doping type and the second doping type have opposite conductivity types, the first well region is provided with a Schottky junction on a surface thereof, the Schottky junction is located between the first gate lead-out region and the drain lead-out region, and the Schottky junction is isolated from the first gate lead-out region and the drain lead-out region by an isolation structure.

2. The junction field effect transistor according to claim 1 , wherein the first doping type is N-type, the second doping type is P-type.

3. The junction field effect transistor according to claim 2 , wherein the second doping type buried layer comprises a buried P-type well and a P-type island, the buried P-type well extends from a position beneath the second well region to a position beneath the first well region, the P-type island is located beneath the first well region and is isolated from buried P-type well by the substrate.

4. The junction field effect transistor according to claim 3 , wherein the P-type island and the buried P-type well are formed by the same photolithography and ion implantation step.

5. The junction field effect transistor according to claim 1 , further comprising a second doping type implantation region formed in the first well region, wherein the first gate lead-out region is located in the second doping type implantation region.

6. The junction field effect transistor according to claim 1 , wherein the Schottky junction is formed by direct contact of the first well region and metal or metal silicide.

7. The junction field effect transistor according to claim 1 , wherein the isolation structure is a field oxide structure.

8. A method of manufacturing junction field effect transistor, comprising steps as follows:

providing a substrate;

forming a buried layer in the substrate by ion implantation;

forming an epitaxial layer on the buried layer by epitaxy technology;

forming a first well region and a second well region in the epitaxial layer by ion implantation and drive-in;

forming an isolation structure on surfaces of the first well region and the second well region, the isolation structure provides an alignment reference for subsequent formation of a gate electrode, a source electrode and a drain electrode;

forming a gate structure comprising a first gate lead-out region formed in the first well region, a second gate lead-out region formed in the second well region, a gate oxide formed on the first gate lead-out region and the second gate lead-out region, and a polysilicon gate formed on the gate oxide;

forming a source lead-out region and a drain lead-out region in the first well region by ion implantation;

activating implanted ions by thermal annealing; and

forming a metal or alloy structure on the first well region, wherein a portion of the isolation structure between first gate lead-out region and the drain lead-out region has a discontinuous structure, thereby enabling the metal or alloy structure in the region to directly contact the first well region below to form a Schottky junction,

wherein the substrate has a second doping type, the buried layer comprises a second doping type buried layer, the first well region has a first doping type, the second well region has the second doping type, the first gate lead-out region and the second gate lead-out region have the second doping type, the source lead-out region and the drain lead-out region have the first doping type, the first doping type and the second doping type have opposite conductivity types.

9. The method according to claim 8 , wherein the first doping type is N-type, the second doping type is P-type.

10. The method according to claim 9 , wherein forming the buried layer in the substrate by ion implantation comprises: defining implantation windows of a buried P-type well and a P-type island by photolithography, forming the P-type island beneath a first region which will be the first well region and the buried P-type well which extends from a position beneath a second region which will be the second well region to a position beneath the first region by ion implantation, wherein the P-type island and the buried P-type well are isolated by the substrate.

11. The method according to claim 8 , wherein after forming the isolation structure on surfaces of the first well region and the second well region, and prior to forming the gate structure, the method further comprises: forming a second doping type implantation region in the first well region by ion implantation, wherein the first gate lead-out region is located in the second doping type implantation region.

12. The method according to claim 8 , wherein the isolation structure is a field oxide structure.

13. The method according to claim 8 , wherein forming the gate structure further comprises forming a sidewall structure on a sidewall of the polysilicon gate.