Sleek serial interface for a wrapper boundary register (device and method)
Invention achieves reduced amount of terminals to control a test mode, test function and test results of a given standard for at least one “wrapped core” ( 40,100 ) (a core 100 surrounded by a wrapper boundary register ( 40 ) as “wrapper chain”). Test flexibility and speed of testing the core ( 100 ) are also improved. Suggested serial test interface comprises a state machine ( 210 ) and an instruction register ( 213 ) for wrapper-instructions, supplied through a single physical data input terminal ( 1 a ). The state machine ( 210 ) reads wrapper-instructions held by the instruction register ( 213 ) and generates on-chip wrapper control signals ( 30 ) of the given standard for the wrapper boundary register ( 40 ) of the core ( 100 ). At least one wrapper-instruction read from the Instruction Register ( 213 ) provides at least one wrapper control signal ( 30 ). The single input terminal ( 1 a ) also supplies an input test signal SDI for coupling to the wrapper boundary register ( 40 ) as on chip logical input test signal WSI. A single output terminal ( 1 b ) returns an output test signal SDO from an output WSO of the wrapper boundary register ( 40 ). Invention may apply to IEEE 1500 control signals.
1. A serially operable interface device on a chip ( 1 ), the interface device ( 201 ) for generating control signals for a Wrapper Boundary Register ( 40 , WBR) on chip ( 1 ) level, said wrapper control signals ( 30 ) complying with a given standard for testing a core device ( 100 ), said core device provided on the chip ( 1 ) as well and having the Wrapper Boundary Register, the serial interface device ( 201 ) comprising:
one physical Data Input ( 2 a ) and one physical Data Output ( 2 b ) and no more than the input (SDI) for and the output (SDO) of the serial interface device ( 201 ) are coupled to a respective terminal ( 1 a , 1 b ) on said chip ( 1 ) containing the interface device ( 201 ) and the core device ( 100 ) with the Wrapper Boundary Register;
a physical Clock Input ( 2 c ) that is coupled to a third terminal ( 1 c ) on said chip ( 1 ) on chip level for supplying a clock signal (SCLK) to the serial interface device ( 201 );
an Address Register ( 214 ) for holding a received address for comparison to a device-address ( 214 a );
an Instruction Register ( 213 ) to receive and hold wrapper-instructions supplied through the terminal ( 1 a ) supplying the Data Input (SDI) on said chip ( 1 );
a control logic ( 209 ) including a state machine ( 210 ) for handling transactions from an external master ( 10 ) that supplies logical data input (SDI) to physical data input terminal ( 1 a ) and the serial interface device ( 201 ) returns logical data output (SDO) to said physical data output terminal ( 2 b ) and for said external master ( 10 ) from the Wrapper Boundary Register ( 40 ) of the core device ( 100 );
wherein the state machine ( 210 ) is configured to generate the wrapper control signals ( 30 ) of the given standard for the core device ( 100 ) having the Wrapper Boundary Register; and
read an address held by the Address Register ( 214 ) and compare it to the device-address ( 214 a );
read a currently active wrapper-instruction, held by the Instruction Register ( 213 ); and
send the logic output test (SDO), as taken from the Wrapper Boundary Register.
2. The device of claim 1 , further having a counter ( 211 ) to control a data transmission size in certain states of the state machine ( 210 ), the counter receiving the clock signal (SCLK) supplied to the serial interface device.
3. The device of claim 1 , the state machine ( 210 ) handling transactions between the external master ( 10 ) and itself, wherein the state machine ( 210 ) is capable to generate an additional Wrapper Boundary Register control signal (WT), e.g. WCH_RESET, to and for the Wrapper Boundary register of the core device ( 100 ).
4. The device of claim 1 , wherein the State Machine ( 210 ) is configured and capable to generate all Wrapper Boundary Register control signals ( 30 ; CW, SW, UW, WN) of the given standard, and the SelectWIR signal of the IEEE 1500 standard not being a Wrapper Boundary Register control signal.
5. The device of claim 1 , wherein the state machine ( 210 ) generates at least some Wrapper Boundary Register control signals ( 30 ) comprising one or more of the control signals for the IEEE 1500 Wrapper Boundary Register.
6. The device of claim 1 , wherein an output signal (WSO) of the Wrapper Boundary Register is supplied to the serial interface device ( 201 ) or directly to the terminal ( 2 b ) of the physical Data Output (SDO).
7. The device of claim 1 , wherein the logical data input signal (SDI) at physical Data Input Terminal ( 1 a ) is supplied to the WBR ( 40 ) as Input Signal (WSI).
8. The device of claim 1 , wherein the clock signal (SCLK) from the third terminal ( 1 c ) is also supplied to the Wrapper Boundary Register as clock signal (WRCK).
9. The device of claim 1 , wherein the clock signal (SCLK) from the third terminal ( 1 c ) is supplied to the serial interface device ( 201 ).
10. The device of claim 1 , wherein the logical data input signal (SDI) at physical Data Input Terminal ( 1 a ) is supplied to the Address Register ( 214 ), the Instruction Register ( 213 ) and to the control logic ( 209 ) containing the state machine ( 210 ), but not to the state machine ( 210 ).
11. The device of claim 1 , wherein the coupling is an electrical conductive connection.
12. The device of claim 1 , further having an Identification Register ( 215 ) containing an identification-code ( 215 a ) of the core device ( 100 ).
13. The device of claim 1 , the serial interface device ( 201 ) further having an additional device-address source, supplying a device-address ( 214 a ) of a corresponding core device ( 100 a ) associated with the interface device, when multiple w cores ( 100 a , 100 b ) are on the chip ( 1 ) and each core has an own dedicated serial interface device ( 201 a , 201 b ).
14. The device of claim 1 , further having a counter ( 211 ), supplied with the clock signal (SCLK) through the third terminal ( 1 c ) to control the changes of states ( 510 , 520 , 525 , 530 , 550 ) of the state machine ( 210 ).
15. A serially operable interface device on a chip, the interface device ( 201 ) for generating control signals for a Wrapper Boundary Register on chip, said wrapper control signals ( 30 ) complying with a given standard for testing a core device ( 100 ), said core device provided on the chip ( 1 ) as well and having the Wrapper Boundary Register, the chip comprising:
one physical Data Input ( 1 a ) for test purposes and one physical Data Output ( 1 b ) for test purposes and no more than an input and an output terminal of the serial interface device ( 201 ) are coupled to the terminals ( 1 a , 1 b ) on said chip containing the interface device ( 201 ) and the core device ( 100 ) with the Wrapper Boundary Register,
and a physical Clock Input ( 1 c ) for test purposes that is coupled to a third terminal ( 1 c ) on said chip on chip level for supplying a clock signal (SCLK) to the serial interface device ( 201 );
the serial interface device ( 201 ) on chip further comprising an Instruction Register ( 213 ) to receive and hold wrapper-instructions supplied through the physical data input terminal ( 1 a );
wherein the state machine is configured to:
read a currently active wrapper-instruction, as held by the Instruction Register ( 213 );
generate and provide on-chip wrapper control signals ( 30 ) of the given standard for the core device ( 100 ) having the Wrapper Boundary Register according to the wrapper-instruction read from the Instruction Register.
16. The device of claim 15 , the serial interface device ( 201 ) further having an Address Register ( 214 ) to receive and hold an address supplied through the physical data input terminal ( 1 a ) for comparison with an individual device-address ( 214 a ) of this serial interface device ( 201 a ) and a corresponding core ( 100 a ), when multiple serial interface devices ( 201 a , 201 b , 201 c ) each attributed to a corresponding core ( 100 a , 100 b , 100 c ) are present on the chip ( 1 *).
17. The device of claim 15 , wherein the control logic ( 209 ) has access to an Address Register ( 214 ), being configured for holding a received address, the control w logic ( 209 ) being configured for reading the address as held by the Address Register ( 214 ).
18. The device of claim 15 , further having a counter ( 211 ), supplied with the clock signal (SCLK) through the third terminal ( 1 c ) to control at least some changes of states ( 510 , 520 , 525 , 530 , 550 ) of the state machine ( 210 ).
19. The device of claim 15 , wherein at least some changes of states of the state machine ( 210 ) depend at least from a counter value of the counter ( 211 ) and a wrapper-instruction as read from the Instruction Register ( 213 ), the Instruction Register ( 213 ) having received the wrapper-instruction through the physical data input terminal ( 1 a ).
20. The device of claim 15 , further having an Identification Register ( 215 ) for holding an ID-Code ( 215 a ) identifying the core device ( 100 ).
21. The device of claim 20 , the ID-Code of the Identification Register ( 215 ) identifying the core device ( 100 ) is sent by control of the state machine ( 210 ) and a control logic ( 209 ) in the serial test interface ( 201 ) to the single output terminal ( 1 b ) to the external master ( 10 ), upon an corresponding wrapper-instruction as read from the 3D Instruction Register ( 213 ).
22. The device of claim 21 , the control logic ( 209 ) in the serial test interface ( 201 ) acts as gateway to the single output terminal ( 1 b ) for supplying either—but not both a the same time—the ID-Code ( 215 a ) of the Identification Register ( 215 ) or the logical output test signal (WSO) returning from the Wrapper Boundary Register of the core device ( 100 ) to the external master ( 10 ) by control of the control logic ( 209 ) upon an corresponding wrapper-instruction as read from the Instruction Register ( 213 ).
23. The device of claim 15 , further having a power-on detector ( 20 ) for supplying a power on reset signal to the serial test interface ( 201 ) and the Wrapper Boundary Register of the core ( 100 ) for common initialization.
24. The device of claim 15 , the clock signal (SCLK) supplied through the third terminal ( 1 c ) is supplied to the Wrapper Boundary Register and the serial test interface ( 201 ).
25. A method of testing wrapped cores within a System-on-Chip, comprising:
each wrapped core of the wrapped cores having an associated serial interface device;
each interface device having a unique device address, not being the same, although a structure of all serial interface devices is the same;
each serial interface device further having an Address Register, receiving and holding an address supplied through a test input terminal; and
each serial interface device comparing the supplied address with an individual interface device-address as the unique device address of each serial interface device for the associated wrapped core on the System-on-Chip;
whereby electing a serial interface device having a device address that matches the supplied address held by the Address Register.
26. The method of claim 25 , wherein each serial interface device ( 201 a , 201 b , 201 c ) having a structure comprising:
one physical Data Input ( 2 a ) and one physical Data Output ( 2 b ) and no more than the input (SDI) for and the output (SDO) of the serial interface device ( 201 ) are coupled to a respective terminal ( 1 a , 1 b ) on said chip ( 1 ) containing the interface device ( 201 ) and the core device ( 100 ) with the Wrapper Boundary Register ( 40 ); and a physical Clock Input ( 2 c ) that is coupled to a third terminal ( 1 c ) on said chip ( 1 ) on chip level for supplying a clock signal (SCLK) to the serial interface device ( 201 );
an Address Register ( 214 ) for holding a received address for comparison to a device-address ( 214 a );
an Instruction Register ( 213 ) to receive and hold wrapper-instructions supplied through the terminal ( 1 a ) supplying the Data Input (SDI) on said chip ( 1 ); and
a control logic ( 209 ) including a state machine ( 210 ) for handling transactions from an external master ( 10 ) that supplies logical data input (SDI) to physical data input terminal ( 1 a ) and the serial interface device ( 201 ) returns logical data output (SDO) to said physical data output terminal ( 2 b ) and for said external master ( 10 ) from the WBR ( 40 ) of the core device ( 100 ).
27. The device of claim 2 , wherein the certain states are READ_DEV_ADR, READ_INSTRUCTION, SEND_IDCODE, READ_DATA and READ_UPDATE.
28. The device of claim 7 , wherein the logical data input signal (SDI) at physical Data Input Terminal is directly supplied to the WBR as Input Signal (WSI).
29. The device of claim 8 , wherein the clock signal (SCLK) from the third terminal is directly supplied to the Wrapper Boundary Register as clock signal (WRCK).
30. The device of claim 9 , wherein the clock signal (SCLK) from the third terminal is supplied to the serial interface device, therewith to the control logic containing the state machine, the Address Register and the Instruction Register.
31. The device of claim 4 , wherein the given standard is CaptureWR, ShiftWR, UpdateWR and WRSTN of the IEEE 1500 standard, the SelectWIR signal of the IEEE 1500 standard not being a WBR control signal.