IP Library Granted Patent US 10,134,598
Granted Patent B2
US 10,134,598 · App. 15/321,245 · Granted Nov 20, 2018

Method for manufacturing semiconductor device

Inventors: Kazunari Nakata (Tokyo, JP); Tamio Matsumura (Tokyo, JP); Yoshiaki Terasaki (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H01L21/304B24B7/228B24B27/0023B24B49/12H01L21/30604H01L21/6836H01L22/20H01L22/12H01L2221/6834H01L2221/68327
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Quick Facts
Patent No.
US 10,134,598
App. No.
15/321,245
Granted
Nov 20, 2018
Kind
B2
Abstract

As a first grinding step, a peripheral portion of a back surface of a wafer ( 1 ) is ground with a first grindstone ( 17 ) to form a fractured layer ( 19 ) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer ( 1 ) is ground with the first grindstone ( 17 ) to form a recess ( 21 ) while the peripheral portion in which the fractured layer ( 19 ) is formed is left as a rib ( 20 ). Subsequently, as a third grinding step, a bottom surface of the recess ( 21 ) is ground with a second grindstone ( 22 ) of an abrasive grain size smaller than that of the first grindstone ( 17 ) to reduce a thickness of the wafer ( 1 ).

Claims (14)

1. A method for manufacturing a semiconductor device comprising:

a step of forming a plurality of semiconductor devices in a front surface of a wafer;

a first grinding step of grinding a peripheral portion of a back surface of the wafer with a first grindstone to form a fractured layer in the peripheral portion while a central portion of the back surface of the wafer is not ground and is left as an unground region in the first grinding step;

a second grinding step of grinding the central portion of the back surface of the wafer with the first grindstone to form a recess while the peripheral portion in which the fractured layer is formed is left as a rib; and

a third grinding step of grinding a bottom surface of the recess with a second grindstone of an abrasive grain size smaller than that of the first grindstone to reduce a thickness of the wafer.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising a step of removing the fractured layer by wet etching after the third grinding step.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein

a relative position between the first grindstone and the wafer is changed and the unground region is ground in the second grinding step.

4. The method for manufacturing a semiconductor device according to claim 3 , wherein a position of the first grindstone in the second grinding step is determined on the basis of a measured value of a width of the unground region.

5. The method for manufacturing a semiconductor device according to claim 4 , wherein an image of the wafer is subjected to image processing to measure the width of the unground region.

6. The method for manufacturing a semiconductor device according to claim 4 , wherein a step of the unground region is measured along a diameter direction of the wafer to obtain the width of the unground region.

7. The method for manufacturing a semiconductor device according to claim 1 , wherein an amount of grinding in the step of providing the fractured layer is 1 μm or more.

8. The method for manufacturing a semiconductor device according to claim 1 , wherein an average grain size of the first grindstone is equal to or larger than 20 μm and equal to or smaller than 100 μm.

9. The method for manufacturing a semiconductor device according to claim 1 , wherein an average grain size of the second grindstone is equal to or smaller than 10 μm.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2020
From: MITSUBISHI ELECTRIC CORPORATION
To: ROHM CO., LTD.
Reel/Frame 054505/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2016
From: NAKATA, KAZUNARI; MATSUMURA, TAMIO; TERASAKI, YOSHIAKI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 040744/0163 →
Continuity (1)
Related Publication 20170200613A1 · Jul 13, 2017