RRAM array with current limiting element to enable efficient forming operation
An RRAM circuit having a current limiting element configured to improve forming time of RRAM cells, and an associated method of formation, is disclosed. In some embodiments, the RRAM circuit has an RRAM array with a plurality of RRAM devices. A bit-line decoder is configured to concurrently apply a forming signal to a plurality of bit-lines coupled to two or more of the plurality of RRAM devices in a row of the RRAM array. A current limiting element is configured to concurrently limit a current on the plurality of bit-lines to below a forming value during a forming operation that forms conductive filaments within the RRAM devices. By limiting the current on the bit-lines during the forming operation, a forming signal can concurrently be applied to multiple RRAM devices while maintaining a relatively low overall power consumption, thereby allowing for the forming operation to be performed quickly.
1. A resistive random access memory (RRAM) circuit, comprising:
a plurality of RRAM cells respectively comprising an RRAM device having a first electrode and a second electrode;
a bit-line decoder configured to concurrently apply a forming signal to a plurality of bit-lines directly connected to the first electrode of two or more of the plurality of RRAM cells; and
a current limiting element directly connected to the second electrode of the two or more of the plurality of RRAM cells, wherein the current limiting element is configured to concurrently limit a current on the plurality of bit-lines to below a forming value during a forming operation that forms an initial conductive filament within the RRAM device.
2. The RRAM circuit of claim 1 , further comprising:
a control unit configured to concurrently operate the current limiting element to limit the current on the plurality of bit-lines and the bit-line decoder to apply the forming signal to the plurality of bit-lines.
3. The RRAM circuit of claim 1 ,
wherein the bit-line decoder is configured to apply a forming voltage to the plurality of bit-lines during the forming operation and to apply a write voltage to one or more of the plurality of bit-lines during a write operation; and
wherein the write voltage is smaller than the forming voltage.
4. The RRAM circuit of claim 1 , wherein the current limiting element comprises:
a plurality of transistor devices respectively having a source terminal operably coupled to one of the plurality of bit-lines.
5. The RRAM circuit of claim 4 , further comprising:
a diode connected transistor having a source terminal, a drain terminal coupled to ground, and a gate terminal coupled to gate terminals of the plurality of transistor devices; and
a current source coupled to the source terminal of the diode connected transistor and the gate terminals of the plurality of transistor devices.
6. The RRAM circuit of claim 1 , further comprising:
one or more additional current limiting elements configured to independently limit a current on one of the plurality of bit-lines during a write operation.
7. The RRAM circuit of claim 1 , wherein for the plurality of RRAM cells respectively the first electrode is directly connected to one of the plurality of bit-lines and the second electrode is connected to a source-line by way of an access transistor, wherein a gate terminal of the access transistor is directly connected to a word-line.
8. The RRAM circuit of claim 7 , wherein the current limiting element comprises:
a plurality of transistor devices respectively comprising a source terminal directly connected to the source-line;
a diode connected transistor having a source terminal, a drain terminal directly connected to ground, and a gate terminal directly connected to gate terminals of the plurality of transistor devices; and
a current source directly connected to the source terminal of the diode connected transistor and the gate terminals of the plurality of transistor devices.
9. The RRAM circuit of claim 7 , further comprising:
a sensing circuitry configured to be operably decoupled from the plurality of bit-lines during the forming operation and to be operably coupled to the plurality of bit-lines during a read operation.
10. The RRAM circuit of claim 1 , wherein the current limiting element limits the current on the plurality of bit-lines below 5 λA.
11. A resistive random access memory (RRAM) circuit, comprising:
a plurality of RRAM cells, respectively comprising a first electrode directly connected to a bit-line and a second electrode connected to a source-line by way of an access transistor;
a bit-line decoder configured to concurrently apply a forming signal to a plurality of bit-lines directly connected to the first electrode of two or more of the plurality of RRAM cells during a forming operation; and
a current limiting element configured to limit currents on the plurality of bit-lines to a smaller current value during the forming operation than during a write operation, wherein the current limiting element comprises:
a plurality of transistor devices respectively comprising a source terminal directly connected to the source-line of the two or more of the plurality of RRAM cells;
a diode connected transistor having a source terminal, a drain terminal directly connected to ground, and a gate terminal directly connected to gate terminals of the plurality of transistor devices; and
a current source directly connected to the source terminal of the diode connected transistor and the gate terminals of the plurality of transistor devices.
12. The RRAM circuit of claim 11 ,
wherein the bit-line decoder is configured to apply a forming voltage to the plurality of bit-lines during the forming operation and to apply a write voltage to one or more of the plurality of bit-lines during the write operation; and
wherein the write voltage is smaller than the forming voltage.
13. The RRAM circuit of claim 11 , wherein the first electrode is separated from the second electrode by a high-k dielectric layer.
14. The RRAM circuit of claim 11 , further comprising:
a control unit configured to operate the current source to output a first reference current during the forming operation and to output a second reference current during a read operation and the write operation.
15. The RRAM circuit of claim 11 , further comprising:
a sensing circuitry configured to be operably decoupled from the plurality of bit-lines during the forming operation and to be operably coupled to the plurality of bit-lines during a read operation.
16. The RRAM circuit of claim 11 , further comprising:
one or more additional current limiting elements configured to independently limit a current on one of the plurality of bit-lines during the write operation.
17. A method of performing a forming operation on an RRAM circuit, comprising:
activating a word-line operably coupled to a row of RRAM cells within an RRAM array;
concurrently applying a forming signal to a plurality of bit-lines coupled to a plurality of RRAM cells within the row of RRAM cells to perform a forming operation that forms initial conductive filaments within the plurality of RRAM cells; and
concurrently limiting a current of the forming signal on the plurality of bit-lines to below a forming value during the forming operation, wherein the current of the forming signal is smaller than a current value used to perform a write operation on the plurality of RRAM cells.
18. The method of claim 17 , further comprising:
applying the forming signal, which comprises a forming voltage, to the plurality of bit-lines, wherein the plurality of bit-lines are coupled to a first electrode of the plurality of RRAM cells; and
applying a second voltage smaller than the forming voltage to a plurality of source-lines, wherein the plurality of source-lines are coupled to a second electrode of the plurality of RRAM cells.
19. The method of claim 18 , further comprising:
operably decoupling a sensing circuit from the plurality of bit-lines during the forming operation.
20. The method of claim 18 , further comprising:
concurrently applying the forming voltage to all of the bit-lines of the RRAM array.