Semiconductor memory device, structure and methods
A multilevel semiconductor device, including: a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor.
1. A multilevel semiconductor device, comprising:
a first level comprising a first array of first memory cells;
a second level comprising a second array of second memory cells, said first level is overlaid by said second level,
wherein at least one of said first memory cells comprises a vertically oriented first transistor, and
wherein at least one of said second memory cells comprises a vertically oriented second transistor, and
wherein said first transistor comprises a first single crystal channel, and
wherein said second transistor comprises a second single crystal channel, and
wherein said first transistor is self aligned to said second transistor,
wherein said first transistor comprises a charge trap gate stack,
wherein said first level comprises at least one memory bit-line, and
wherein said bit-line is shared between said first level and said second level, and
wherein said bit-line is connected to an inline staircase structure.
2. A multilevel semiconductor device, comprising:
a first level comprising a first array of first memory cells;
a second level comprising a second array of second memory cells, said first level is overlaid by said second level,
wherein at least one of said first memory cells comprises a vertically oriented first transistor, and
wherein at least one of said second memory cells comprises a vertically oriented second transistor, and
wherein said first transistor comprises a first single crystal channel, and
wherein said second transistor comprises a second single crystal channel, and
wherein said first transistor is self aligned to said second transistor,
wherein said first transistor comprises a charge trap gate stack,
wherein said first level comprises at least one memory bit-line, and
wherein said bit-line is shared between said first level and said second level, and
wherein said bit-line is connected to a staircase structure disposed perpendicularly with respect to said bit-line.
3. A multilevel semiconductor device, comprising:
a first level comprising a first array of first memory cells;
a second level comprising a second array of second memory cells, said first level is overlaid by said second level,
wherein at least one of said first memory cells comprises a vertically oriented first transistor, and
wherein at least one of said second memory cells comprises a vertically oriented second transistor, and
wherein said first transistor comprises a first single crystal channel, and
wherein said second transistor comprises a second single crystal channel, and
wherein said first transistor is self aligned to said second transistor,
wherein said first transistor comprises a charge trap gate stack,
wherein said first channel comprises at least 5% Ge atoms.