IP Library › Granted Patent US 9,900,482

Granted Patent B2

US 9,900,482 · App. 15/335,778 · Granted Feb 20, 2018

Solid-state imaging element and camera system

Inventor: Yusuke Oike (Kanagawa, JP)

Assignee: Sony Corporation

H04N5/2253 H01L27/1464 H01L27/14612 H01L27/14634 H01L27/14636 H01L27/14641 H01L27/14643 H04N5/341 H04N5/378 H04N5/3741 H04N5/3742 H04N5/3745 H04N5/37457

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Quick Facts

Patent No.: US 9,900,482
App. No.: 15/335,778
Granted: Feb 20, 2018
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A solid-state imaging element that includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that include a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals from the signal output part of the pixel cells are propagated, in which the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells are arrayed in a two-dimensional shape, the signal output part of a pixel group formed with the plurality of pixel cells shares an output signal line wired from the stack-connecting parts, and the output signal line has a separation part which can separate each output signal line.

Claims (97)

1. An imaging device comprising:

a first substrate including:

a first plurality of pixels, wherein each pixel of the first plurality of pixels includes an amplification transistor and a selection transistor,

a first signal line coupled to the selection transistor of each pixel of the first plurality of pixels,

a second plurality of pixels, wherein each pixel of the second plurality of pixels includes an amplification transistor and a selection transistor,

a second signal line coupled to the selection transistor of each pixel of the second plurality of pixels,

a third plurality of pixels, wherein each pixel of the third plurality of pixels includes an amplification transistor and a selection transistor,

a third signal line coupled to the selection transistor of each pixel of the third plurality of pixels,

a fourth plurality of pixels, wherein each pixel of the fourth plurality of pixels includes an amplification transistor and a selection transistor,

a fourth signal line coupled to the selection transistor of each pixel of the fourth plurality of pixels,

a first wiring layer disposed at a side opposite to a light incident side of the first substrate,

a first transistor, wherein a first terminal of the first transistor is coupled to the first signal line and a second terminal of the first transistor is coupled to a ground,

a second transistor, wherein a first terminal of the second transistor is coupled to the second signal line and a second terminal of the second transistor is coupled to the ground,

a first switch circuit coupled to the first signal line and the second signal line, and

a second switch circuit coupled to the third signal line and the fourth signal line; and

a second substrate including:

at least a portion of an A/D conversion unit, and

a second wiring layer,

wherein,

the first substrate is bonded to the second substrate through a first via and a second via,

the first switch circuit is configured to selectively couple the first signal line and the second signal line to the first via, and

the second switch circuit is configured to selectively couple the third signal line and the fourth signal line to the second via.

2. The imaging device according to claim 1 , wherein at least one pixel of the first plurality of pixels includes a plurality of photoelectric conversion elements, a transfer transistor, a reset transistor, an amplifier transistor, and a select transistor.

3. The imaging device according to claim 1 , further comprising:

a third switch circuit coupled to the third signal line, wherein the third switch circuit is configured to selectively couple the third signal line to the second via.

4. The imaging device according to claim 3 , wherein the first switch circuit includes a fourth switch circuit coupled to the first signal line and the first via, and a fifth switch circuit coupled to the second signal line and the first via.

5. The imaging device according to claim 1 , wherein the first wiring layer includes the first signal line and the second signal line.

6. An imaging device comprising:

a first substrate including:

a first plurality of pixels, wherein each pixel of the first plurality of pixels includes an amplification transistor and a selection transistor,

a first signal line coupled to the selection transistor of each pixel of the first plurality of pixels,

a second plurality of pixels, wherein each pixel of the second plurality of pixels includes an amplification transistor and a selection transistor,

a second signal line coupled to the selection transistor of each pixel of the second plurality of pixels,

a third plurality of pixels, wherein each pixel of the third plurality of pixels includes an amplification transistor and a selection transistor,

a third signal line coupled to the selection transistor of each pixel of the third plurality of pixels,

a fourth plurality of pixels, wherein each pixel of the fourth plurality of pixels includes an amplification transistor and a selection transistor, and

a fourth signal line coupled to the selection transistor of each pixel of the fourth plurality of pixels,

a first wiring layer disposed at a side opposite to a light-incident side of the first substrate,

a first switch circuit coupled to the first signal line and the second signal line,

a second switch circuit coupled to the third signal line and the fourth signal line; and

a second substrate including:

at least a portion of an A/D conversion unit, and

a second wiring layer,

wherein,

the first substrate is bonded to the second substrate through a first via and a second via, a first terminal of a first transistor is coupled to the first signal line and a second terminal of the first transistor is coupled to a ground, a first terminal of a second transistor is coupled to the second signal line and a second terminal of the second transistor is coupled to the ground, the first switch circuit is configured to selectively couple the first signal line and the second signal line to the first via, and the second switch circuit is configured to selectively couple the third signal line and the fourth signal line to the second via.

7. The imaging device according to claim 6 , wherein at least one pixel of the first plurality of pixels includes a plurality of photoelectric conversion elements, a transfer transistor, a reset transistor, an amplifier transistor, and a select transistor.

8. The imaging device according to claim 6 , further comprising:

a third switch circuit coupled to the third signal line, wherein the third switch circuit is configured to selectively couple the third signal line to the second via.

9. The imaging device according to claim 8 , wherein the first switch circuit includes a fourth switch circuit coupled to the first signal line and the first via, and a fifth switch circuit coupled to the second signal line and the first via.

10. The imaging device according to claim 6 , wherein the first wiring layer includes the first signal line and the second signal line.

11. The imaging device according to claim 6 , wherein the first substrate includes the first transistor and the second transistor.

12. An imaging device comprising: