IP Library Granted Patent US 11,664,447
Granted Patent B2
US 11,664,447 · App. 15/336,763 · Granted May 30, 2023

Semiconductor device and a method of making a semiconductor device

Inventors: Jeroen Croon (Waalre, NL); Coenraad Cornelis Tak (San Jose, CA)
Assignee: Nexperia B.V.
H01L29/778H01L23/495H01L23/552H01L23/49562H01L23/49805H01L25/0655H01L29/2003H01L29/7786H01L29/78H01L2224/32225H01L2224/32245H01L2224/48091H01L2224/48227H01L2224/48237H01L2224/48247H01L2224/73265H01L2924/15313H01L2924/181H01L2924/19107
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Quick Facts
Patent No.
US 11,664,447
App. No.
15/336,763
Granted
May 30, 2023
Kind
B2
Abstract

A semiconductor device and a method of making the same. The device includes a substrate mounted on a carrier, the substrate comprising a High Electron Mobility Transistor (HEMT) having a source, a gate and a drain. The carrier comprises an electrically conductive shielding portion for providing shielding against electromagnetic interference associated with switching of the device during operation. The electrically conductive shielding portion is electrically isolated from the source and from the backside of the substrate.

Claims (27)

1. A semiconductor device, comprising a substrate mounted on a carrier, the substrate comprising:

a High Electron Mobility Transistor (HEMT) having a source, a gate, a drain and an electrically conductive backside,

wherein the carrier comprises an electrically conductive shielding portion configured to provide shielding against electromagnetic interference associated with switching of the semiconductor device during operation and an electrically conductive upper surface,

wherein the electrically conductive shielding portion is electrically isolated from the source and from an electrically conductive backside of the substrate,

wherein the electrically conductive backside of the substrate is mounted directly on the electrically conductive upper surface of the carrier; and

wherein the electrically conductive shielding portion is electrically connected to the drain.

2. The semiconductor device of claim 1 , wherein the electrically conductive shielding portion extends at least partially beneath the substrate.

3. The semiconductor device of claim 1 , wherein the electrically conductive shielding portion extends around a periphery of the substrate, when viewed from above a major surface of the substrate, to at least partially surround the substrate.

4. The semiconductor device of claim 1 , wherein the electrically conductive shielding portion is electrically connected to an external potential.

5. The semiconductor device of claim 1 , wherein the carrier comprises a dielectric substrate having one or more metal layers.

6. The semiconductor device of claim 5 , wherein the backside of the substrate is mounted on the electrically conductive upper surface of a metal layer located on an upper surface of the dielectric substrate and wherein the electrically conductive shielding portion comprises one or more metal layers located beneath the upper surface of the dielectric substrate.

7. The semiconductor device of claim 1 , wherein the carrier comprises a metallic lead frame.

8. The semiconductor device of claim 1 , wherein the carrier comprises a printed circuit board having one or more patterned metal features located on a surface of the printed circuit board, wherein at least one of the patterned metal features forms the electrically conductive shielding portion.

9. The semiconductor device of claim 1 , wherein the carrier comprises an electrically conductive platform having the electrically conductive upper surface upon which the backside of the substrate is mounted, wherein the source is electrically connected to the electrically conductive platform to electrically connect the source to the backside of the substrate, and wherein the electrically conductive platform is electrically isolated from the electrically conductive shielding portion.

10. The semiconductor device of claim 9 , wherein the electrically conductive platform is electrically connected to a source output terminal of the semiconductor device.

11. The semiconductor device of claim 9 , further comprising:

a package for the semiconductor device, and

a second semiconductor substrate including a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) packaged together with the semiconductor device, wherein the second semiconductor substrate is also mounted on the electrically conductive platform.

12. The semiconductor device of claim 1 , wherein the backside of the substrate is electrically connected to the source.

13. A high-side switch comprising a semiconductor device according to claim 1 .

14. A method of making a semiconductor device, the method comprising:

providing a substrate comprising a High Electron Mobility Transistor having a source, a gate, a drain and an electrically conductive backside; and

mounting the substrate on a carrier;

wherein the carrier comprises an electrically conductive shielding portion configured to provide shielding against electromagnetic interference associated with switching of the device during operation and an electrically conductive upper surface,

wherein the electrically conductive shielding portion is electrically isolated from the source and from an electrically conductive backside of the substrate;

wherein the electrically conductive backside of the substrate is mounted to the electrically conductive upper surface of the carrier, and

wherein the electrically conductive shielding portion is electrically connected to the drain.

Assignments (3)
CHANGE OF ADDRESS Recorded Oct 25, 2018
From: NEXPERIA B.V.
To: NEXPERIA B.V.
Reel/Frame 047310/0449 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2017
From: NXP B.V.
To: NEXPERIA B.V.
Reel/Frame 041002/0454 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2016
From: CROON, JEROEN; TAK, COENRAAD CORNELIS
To: NXP B.V.
Reel/Frame 040508/0257 →
Priority Claims (1)
EP 15194122 · Nov 11, 2015 · regional
Continuity (1)
Related Publication 20170133303A1 · May 11, 2017