Method, apparatus and system for automatically performing end-to-end channel mapping for an interconnect
In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.
1. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a design tool cause the design tool to perform a method comprising:
receiving, in the design tool, communication profile information regarding a system on chip (SoC) undergoing a design process, the SoC to comprise a plurality of intellectual property (IP) logics to be interconnected by a fabric including a plurality of fabric segments, the communication profile information including, at least, source channel information for a source IP logic and sink channel information for a sink IP logic;
performing a channel mapping between the source IP logic and the sink IP logic through the plurality of fabric segments according to the communication profile information;
updating a data structure based on the channel mapping, to form an intermediate representation of at least a portion of the SoC; and
creating a configuration file using the data structure, and fabricating the SoC using the configuration file.
2. The non-transitory machine-readable medium of claim 1 , wherein performing the channel mapping comprises, responsive to a first link mapping request of the communication profile information, performing an as late as possible channel mapping.
3. The non-transitory machine-readable medium of claim 2 , wherein the as late as possible channel mapping comprises:
mapping a source port of the source IP logic to a source channel associated with the source channel information;
mapping one or more intermediate channels within the plurality of fabric segments to a source channel associated with the source channel information; and
mapping a sink port of the sink IP logic to a sink channel associated with the sink channel information.
4. The non-transitory machine-readable medium of claim 1 , wherein performing the channel mapping comprises, responsive to a second link mapping request of the communication profile information, performing an as soon as possible channel mapping.
5. The non-transitory machine-readable medium of claim 4 , wherein the as soon as possible channel mapping comprises:
mapping a source port of the source IP logic to a source channel associated with the source channel information;
mapping one or more intermediate channels within the plurality of fabric segments to a sink channel associated with the sink channel information; and
mapping a sink port of the sink IP logic to the sink channel associated with the sink channel information.
6. The non-transitory machine-readable medium of claim 1 , wherein performing the channel mapping comprises:
using an end-to-end channel mapping provided by a user when the communication profile information includes the end-to-end channel mapping, the end-to-end channel mapping for a first path, and automatically performing the channel mapping for one or more other paths for which the user did not provide the end-to-end channel mapping.
7. The non-transitory machine-readable medium of claim 1 , wherein when the sink IP logic comprises a peripheral component interconnect express (PCIe) device:
using a first prior channel mapping if the source IP logic, a source channel associated with the source channel information and a corresponding traffic class are specified in the first prior channel mapping;
using a second prior channel mapping if the sink IP logic, a sink channel associated with the sink channel information and a corresponding traffic class are specified in the second prior channel mapping; and
otherwise performing a channel mapping for a link between the source IP logic and the sink IP logic using an as late as possible channel mapping.
8. The non-transitory machine-readable medium of claim 1 , wherein performing the channel mapping comprises sharing at least one channel in at least one of the plurality of fabric segments for:
a first path between the source IP logic and the sink IP logic; and
a second path between a third IP logic and a fourth IP logic.
9. The non-transitory machine-readable medium of claim 1 , wherein performing the channel mapping comprises:
allocating a first channel in a first one of the plurality of fabric segments for a first path between the source IP logic and the sink IP logic; and
allocating a second channel in the first one of the plurality of fabric segments for a second path between the source IP logic and a second IP logic.
10. The non-transitory machine-readable medium of claim 1 , wherein the method further comprises:
enabling a user to move a location of a first IP logic from a first fabric segment of the plurality of fabric segments to a second fabric segment of the plurality of fabric segments; and
automatically adjusting a channel mapping between the first IP logic and a second IP logic based at least in part on the moved location of the first IP logic.
11. A method comprising:
receiving, in a design tool, communication profile information regarding a system on chip (SoC) undergoing a design process, the SoC to comprise a plurality of intellectual property (IP) logics to be interconnected by a fabric including a plurality of fabric segments, the communication profile information including, at least, source channel information for a source IP logic and sink channel information for a sink IP logic;
performing a channel mapping between the source IP logic and the sink IP logic through the plurality of fabric segments according to the communication profile information;
updating a data structure based on the channel mapping, to form an intermediate representation of at least a portion of the SoC; and
creating a configuration file using the data structure, and fabricating the SoC using the configuration file.
12. The method of claim 11 , wherein performing the channel mapping comprises, responsive to a first link mapping request of the communication profile information, performing an as late as possible channel mapping.
13. The method of claim 12 , wherein the as late as possible channel mapping comprises:
mapping a source port of the source IP logic to a source channel associated with the source channel information;
mapping one or more intermediate channels within the plurality of fabric segments to a source channel associated with the source channel information; and
mapping a sink port of the sink IP logic to a sink channel associated with the sink channel information.
14. The method of claim 11 , wherein performing the channel mapping comprises, responsive to a second link mapping request of the communication profile information, performing an as soon as possible channel mapping.
15. The method of claim 14 , wherein the as soon as possible channel mapping comprises:
mapping a source port of the source IP logic to a source channel associated with the source channel information;
mapping one or more intermediate channels within the plurality of fabric segments to a sink channel associated with the sink channel information; and
mapping a sink port of the sink IP logic to the sink channel associated with the sink channel information.
16. The method of claim 11 , wherein performing the channel mapping comprises:
using an end-to-end channel mapping provided by a user when the communication profile information includes the end-to-end channel mapping, the end-to-end channel mapping for a first path, and automatically performing the channel mapping for one or more other paths for which the user did not provide the end-to-end channel mapping.
17. The method of claim 11 , wherein when the sink IP logic comprises a peripheral component interconnect express (PCIe) device, the method further comprises:
using a first prior channel mapping if the source IP logic, a source channel associated with the source channel information and a corresponding traffic class are specified in the first prior channel mapping;
using a second prior channel mapping if the sink IP logic, a sink channel associated with the sink channel information and a corresponding traffic class are specified in the second prior channel mapping; and
otherwise performing a channel mapping for a link between the source IP logic and the sink IP logic using an as late as possible channel mapping.
18. The method of claim 11 , wherein performing the channel mapping comprises sharing at least one channel in at least one of the plurality of fabric segments for:
a first path between the source IP logic and the sink IP logic; and
a second path between a third IP logic and a fourth IP logic.
19. The method of claim 11 , wherein performing the channel mapping comprises:
allocating a first channel in a first one of the plurality of fabric segments for a first path between the source IP logic and the sink IP logic; and
allocating a second channel in the first one of the plurality of fabric segments for a second path between the source IP logic and a second IP logic.
20. The method of claim 11 , wherein the method further comprises:
enabling a user to move a location of a first IP logic from a first fabric segment of the plurality of fabric segments to a second fabric segment of the plurality of fabric segments; and
automatically adjusting a channel mapping between the first IP logic and a second IP logic based at least in part on the moved location of the first IP logic.