Method for reducing crosstalk in CMOS image sensor
View Patent ↗A method of manufacturing a CMOS image sensor includes providing a semiconductor substrate having a front side and a back side, forming at least two pixels in the front side, forming a shallow trench isolation in the front side between the at least two pixels, forming a deep trench in the back side at a location above the shallow trench isolation, and depositing a dielectric layer in the deep trench to form a crosstalk reduction element.
1. A method for manufacturing a CMOS image sensor, the method comprising:
providing a semiconductor substrate having a front side and a back side;
forming at least two pixels in the front side;
forming a shallow trench isolation in the front side between the at least two pixels;
forming a deep trench in the back side at a location above the shallow trench isolation; and
depositing a dielectric layer in the deep trench having a cavity to form a crosstalk reduction element.
2. The method of claim 1 , wherein the deep trench has a ratio of depth/width greater than 5.
3. The method of claim 1 , wherein the deep trench has a depth in a range between 1.5 um and 4 um and a width equal to or less than 0.25 um.
4. The method of claim 1 , wherein the crosstalk reduction element comprises:
a bottom portion in contact with a top portion of the shallow trench isolation; and
a top portion having a surface coplanar with a surface of the back side of the semiconductor device.
5. The method of claim 1 , wherein forming the deep trench in the back side comprises:
forming a mask layer on a surface of the back side;
forming an opening in the mask layer at the location of the shallow trench isolation; and
etching the semiconductor substrate through the opening until a surface of the shallow trench isolation is exposed.
6. The method of claim 1 , wherein depositing the dielectric layer in the deep trench comprises performing a high-aspect ratio depositing process to form the cavity within the deep trench.
7. The method of claim 1 , wherein the dielectric layer comprises sub-atmospheric tetraethyl orthosilicate (SATEOS).
8. The method of claim 1 , wherein the at least two pixels each comprises a photodiode.
9. The method of claim 8 , wherein the photodiode comprises an n+ layer.
10. The method of claim 1 , wherein the cavity comprises a plurality of voids separated from each other.
11. The method of claim 1 , wherein the cavity comprises a near-vacuum structure.
12. The method of claim 1 , wherein the crosstalk reduction element comprises:
a first interface between the semiconductor substrate and the deep trench isolation, the first interface comprising a first total internal reflection angle of about 26 degrees; and
a second interface between the dielectric layer and the cavity, the second interface comprising a second total internal reflection angle of about 17 degrees.
13. The method of claim 1 , further comprising:
Performing a chemical mechanical polishing process on the dielectric layer so that a surface of the dielectric layer is flush with a planar surface of the back side of the semiconductor substrate.