Doping through diffusion and epitaxy profile shaping

1. A method comprising:

etching a semiconductor substrate to form a first trench and a second trench, wherein a remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region;

depositing a doped dielectric layer on sidewalls of the semiconductor region and over a top surface of the semiconductor region, wherein the doped dielectric layer is in physical contact with a semiconductor material of the semiconductor region, and wherein the doped dielectric layer comprises a dopant;

forming a first dielectric region and a second dielectric region in the first trench and the second trench, respectively, wherein the first dielectric region and the second dielectric region overlap bottom portions of the doped dielectric layer;

performing an anneal, wherein the dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region; and

forming a gate stack comprising a gate dielectric and a gate electrode over the gate dielectric, wherein the gate dielectric is in physical contact with the diffused semiconductor region.

2. The method of claim 1 , wherein the semiconductor region comprises a semiconductor base, and semiconductor strips over and connecting to the semiconductor base, and the method further comprises:

etching the semiconductor strips; and

performing an epitaxy from a remaining portion of the semiconductor region to form an epitaxy semiconductor region.

3. The method of claim 2 further comprising:

forming gate spacers on sidewalls of the gate stack;

forming fin spacers on sidewalls of top portions of the semiconductor strips; and

recessing the top portions of the semiconductor strips between the fin spacers, wherein portions of the epitaxy semiconductor region grown from remaining portions of the semiconductor strips merge with each other.

4. The method of claim 2 , wherein the epitaxy is grown from the diffused semiconductor region.

5. The method of claim 1 , wherein the dopant in the doped dielectric layer is of n-type, and the method further comprising forming an additional p-type doped layer, wherein a portion of the additional p-type doped layer overlaps the doped dielectric layer before the anneal.

6. The method of claim 1 , wherein the forming the doped dielectric layer comprises depositing a Phospho-Silicate-Glass (PSG) layer.

7. The method of claim 1 , wherein the forming the doped dielectric layer comprises depositing a Boro-Silicate-Glass (BSG) layer.

8. A method comprising:

etching a semiconductor substrate to form a semiconductor region comprising a semiconductor base and a plurality of semiconductor strips over and connecting to the semiconductor base, wherein a first trench and a second trench extending into the semiconductor substrate are on opposite sides of the semiconductor region;

forming a first doped dielectric layer contacting sidewalls of the semiconductor region, wherein the first doped dielectric layer comprises a portion having a bottom surface contacting a top surface of a bulk portion of the semiconductor substrate, wherein the bulk portion is directly underlying the first trench, and the first doped dielectric layer comprises a first dopant of a first conductivity type;

forming a second doped dielectric layer doped with a second dopant having a second conductivity type opposite to the first conductivity type, wherein the second doped dielectric layer overlaps the first doped dielectric layer;

performing an annealing process to diffuse dopants in both of the first doped dielectric layer and the second doped dielectric layer into each of the plurality of semiconductor strips;

filling the first trench and the second trench with a dielectric material to form isolation regions;

recessing the isolation regions, wherein top portions of the plurality of semiconductor strips form a plurality of semiconductor fins;

forming a gate stack on first portions of the plurality of semiconductor fins;

etching second portions of the plurality of semiconductor fins not covered by the gate stack; and

performing an epitaxy from a remaining portion of the semiconductor region to form an epitaxy source/drain region.

9. The method of claim 8 further comprising:

forming fin spacers on sidewalls of the second portions of the plurality of semiconductor fins; and

recessing the fin spacers when the plurality of semiconductor fins is etched.

10. The method of claim 9 , wherein when the epitaxy is started, the fin spacers have portions remaining, and the remaining portions of the fin spacers are opposite sides of the epitaxy source/drain region after the epitaxy source/drain region is formed, and the remaining portions of the fin spacers are in contact with portions of the plurality of semiconductor fins that are doped with the first dopant and the second dopant to form vertical interfaces.

11. The method of claim 8 , wherein during the annealing process, the second doped dielectric layer is in physical contact with the first doped dielectric layer.

12. The method of claim 8 further comprising forming a first dielectric region and a second dielectric region in the first trench and the second trench, respectively, wherein the first dielectric region and the second dielectric region overlap, and are in contact with, bottom portions of the second doped dielectric layer.

13. The method of claim 8 , wherein the first doped dielectric layer contacts sidewalls of the semiconductor base to form a vertical interface.

14. A method comprising:

etching a semiconductor substrate to form a first semiconductor region and a second semiconductor region separated from each other by trenches;

forming a first doped dielectric layer doped with a first dopant having a first conductivity type, wherein the first doped dielectric layer is formed on sidewalls and top surfaces of the first semiconductor region and the second semiconductor region;

removing portions of the first doped dielectric layer on the first semiconductor region;

forming a second doped dielectric layer doped with a second dopant having a second conductivity type opposite to the first conductivity type, wherein the second doped dielectric layer is formed on sidewalls and top surfaces of the first semiconductor region, and covers remaining portions of the first doped dielectric layer on the second semiconductor region;

filling a dielectric material into the trenches and over the first doped dielectric layer and the second doped dielectric layer; and

performing an anneal, wherein the second dopant is diffused into a first surface layer of the first semiconductor region, and the first dopant is diffused into a second surface layer of the second semiconductor region.

15. The method of claim 14 , wherein the first surface layer of the first semiconductor region is of the second conductivity type, and the second surface layer of the second semiconductor region is of the first conductivity type.

16. The method of claim 15 , wherein the second dopant is also diffused into the second surface layer of the second semiconductor region during the anneal.

17. The method of claim 14 , wherein the forming the first doped dielectric layer comprises depositing a Phospho-Silicate-Glass (PSG) layer.

18. The method of claim 14 , wherein the forming the second doped dielectric layer comprises depositing a boro-Silicate-Glass (BSG) layer.

19. The method of claim 14 further comprises:

removing portions of the first semiconductor region; and

performing an epitaxy to grow an epitaxy region from the first surface layer.

20. The method of claim 1 , wherein the first dielectric region and the second dielectric region are formed after the anneal.