Semiconductor device with enhanced 3D resurf
View Patent ↗A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.
1. A method of fabricating a transistor, the method comprising:
implanting dopant in a first region of a substrate for formation of a drift region; and
forming source and drain regions in second and third regions of the substrate, respectively, the second and third regions being spaced from one another in a first lateral dimension;
wherein charge carriers drift during operation upon application of a bias voltage between the source and drain regions,
the drift region and the drain region are connected to one another at an interface, and
the drift region has a notched boundary in plan view in a second lateral dimension along the interface between the drift region and the drain region.
2. The method of claim 1 , wherein the first region comprises an opening under the third region, the opening comprising the notched boundary.
3. The method of claim 1 , further comprising annealing the substrate such that the drift region is electrically coupled to the drain region.
4. The method of claim 1 , wherein the first and third regions do not laterally overlap.
5. The method of claim 1 , further comprising forming an epitaxial layer of the substrate, wherein the first, second, and third regions are disposed in the epitaxial layer.
6. The method of claim 1 , wherein:
the drift region comprises an opening under the drain region; and
the opening comprises a comb-shaped boundary.
7. The method of claim 1 , wherein the drift region narrows in vertical thickness at the drain region at the interface between the drift region and the drain region.
8. The method of claim 1 , wherein the drift region does not extend laterally across the drain region.
9. The method of claim 1 , wherein:
the drift region comprises an outer section and an inner section surrounded by the outer section and disposed under the drain region; and
the inner section is diminished relative to the outer section such that full depletion of the drift region is attainable during operation.
10. The method of claim 1 , wherein the notched boundary comprises a square wave notch pattern.
11. The method of claim 1 , wherein the notched boundary comprises a periodic notch pattern.
12. The method of claim 1 , wherein:
the semiconductor substrate comprises an epitaxial layer in which the source, drain, and drift regions are formed; and
the drift region is cutoff under the drain region along a notched boundary with the epitaxial layer.
13. The method of claim 1 , further comprising:
forming a trench isolation region in the semiconductor substrate between the source and drain regions, wherein:
the drift region comprises a first region under the trench isolation region and second region under the drain region, and
the drift region has a diminished dopant concentration level in the second region relative to the first region.
14. A method of forming an electronic apparatus, the method comprising:
forming a reduced surface field (RESURF) transistor in a semiconductor substrate by
forming a first semiconductor region having a first conductivity type and in which a channel is formed during operation,
forming second and third semiconductor regions having a second conductivity type and spaced from one another along a first lateral dimension, and
forming a fourth semiconductor region having the second conductivity type and through which charge carriers from the channel formed in the first semiconductor region during operation drift upon application of a bias voltage between the second and third semiconductor regions,
wherein
the third semiconductor region and the fourth semiconductor region are connected to one another at an interface, and
the fourth semiconductor region has a notched boundary in plan view in a second lateral dimension along the interface between the third and fourth semiconductor regions.
15. The method of claim 14 , wherein:
the fourth semiconductor region comprises an opening under the third semiconductor region; and
the opening comprises a comb-shaped boundary.
16. The method of claim 14 , wherein the fourth semiconductor region does not extend laterally across the third semiconductor region.
17. The method of claim 14 , wherein the fourth semiconductor region comprises an outer region and an inner region surrounded by the outer region and disposed under the third semiconductor region; and
the inner region is diminished relative to the outer section such that full depletion of the fourth semiconductor region is attainable during operation.
18. The method of claim 14 , wherein the semiconductor substrate comprises an epitaxial layer in which the first, second, third, and fourth semiconductor regions are formed; and
the fourth semiconductor region is cutoff under the third semiconductor region along a notched boundary with the epitaxial layer.
19. The method of claim 14 , wherein the RESURF transistor further comprises a trench isolation region between the second and third semiconductor regions, wherein:
the fourth semiconductor region comprises a first region under the trench isolation region and a second region under the third semiconductor region; and
the fourth semiconductor region has a diminished dopant concentration level in the second region relative to the first region.