IP Library Granted Patent US 9,941,405
Granted Patent B2
US 9,941,405 · App. 15/340,951 · Granted Apr 10, 2018

Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same

Inventors: Jorge A. Kittl (Austin, TX); Wei-E Wang (Austin, TX); Mark S. Rodder (Dallas, TX)
Assignee: Samsung Electronics Co., Ltd.
H01L29/7848H01L21/30604H01L21/32055H01L21/32133H01L29/0673H01L29/16H01L29/165H01L29/41733H01L29/42392H01L29/456H01L29/66553H01L29/66742H01L29/78618
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Quick Facts
Patent No.
US 9,941,405
App. No.
15/340,951
Granted
Apr 10, 2018
Kind
B2
Abstract

A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.

Claims (27)

1. A method of manufacturing a nanosheet or nanowire device from a stack comprising an alternating arrangement of sacrificial layers and channel layers on a substrate, the method comprising:

deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode; and

forming conductive passivation layers in the electrode recesses, each conductive passivation layer extending at least partially along a side of one of the electrode recesses, wherein portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers; and

epitaxially growing the source and drain electrodes in the electrode recesses, wherein the source and drain electrodes are grown from the substrate and wherein the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.

2. The method of claim 1 , further comprising performing an anisotropic etch to remove portions of the passivation layers covering the substrate at the lower ends of the electrode recesses.

3. The method of claim 1 , wherein the conductive passivation layers extend completely along sides of the electrode recesses.

4. The method of claim 1 , wherein the conductive passivation layers extend only partially along sides of the electrode recesses.

5. The method of claim 1 , further comprising laterally recessing the channel layers before the forming of the conductive passivation layers.

6. The method of claim 1 , further comprising annealing or crystallizing the conductive passivation layers.

7. The method of claim 1 , further comprising:

performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers; and

forming internal spacers in the internal spacer recesses.

8. The method of claim 1 , wherein each conductive passivation layer comprises a conductive oxide.

9. The method of claim 8 , wherein the conductive oxide is RuO 2 or oxygen deficient TiO 2 .

10. The method of claim 1 , wherein each conductive passivation layer has a thickness from approximately 0.2 nm to approximately 2 nm.

11. The method of claim 1 , wherein each conductive passivation layer has a thickness from approximately 0.2 nm to approximately 1 nm.

12. The method of claim 1 , wherein each conductive passivation layer has a thickness from approximately 0.2 nm to approximately 0.5 nm.

13. The method of claim 1 , wherein the epitaxially growing the source and drain electrodes in the electrode recesses comprises repeatedly forming portions grown from the channel layers and portions grown from the substrate and anisotropically etching to selectively remove the portions grown from the channel layers.

14. The method of claim 1 , further comprising:

etching remaining portions of the sacrificial layers to form cavities; and

depositing gate stacks in the cavities.

15. A method of manufacturing a nanosheet or nanowire device from a stack comprising an alternating arrangement of sacrificial layers and channel layers on a substrate, the method comprising:

deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode; and

forming conductive passivation layers in the electrode recesses, each conductive passivation layer extending at least partially along a side of one of the electrode recesses, wherein portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers; and

epitaxially growing the source and drain electrodes in the electrode recesses,

wherein the source and drain electrodes are grown from the substrate and wherein the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers, and

wherein the epitaxially growing the source and drain electrodes in the electrode recesses comprises repeatedly growing portions of the source and drain electrodes and anisotropically etching to selectively remove any portions grown from the channel layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2017
From: KITTL, JORGE A.; WANG, WEI-E; RODDER, MARK S.
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 041538/0467 →
Continuity (2)
Provisional Application 62311305 · Mar 21, 2016
Related Publication 20170271514A1 · Sep 21, 2017