Semiconductor devices having an air gap

1. A semiconductor device, comprising:

a bit line;

a first contact plug disposed on a first side of the bit line;

a second contact plug disposed on a second side of the bit line;

a first air gap disposed between the first contact plug and the bit line;

a second air gap disposed between the second contact plug and the bit line;

a first landing pad electrically connected to the first contact plug and extending from a top end of the first contact plug to cover a first air gap; and

an insulating layer disposed on the second air gap, which is not covered by the first landing pad;

wherein the first landing pad comprises a conductive material.

2. The semiconductor device of claim 1 , further comprising a hard mask pattern disposed on the bit line.

3. The semiconductor device of claim 2 , wherein the first landing pad covers at least a part of the top surface of the hard mask pattern.

4. The semiconductor device of claim 2 , wherein the insulating layer contacts the second air gap and the hard mask pattern.

5. The semiconductor device of claim 1 , wherein an end of the first air gap is disposed between a bottom surface of the first landing pad and a bottom surface of the insulating layer.

6. The semiconductor device of claim 1 , wherein an end of the second air gap is disposed between a bottom surface of the insulating layer and a top surface of the bit line.

7. The semiconductor device of claim 1 , wherein both the first and the second airgaps have line-shapes extending along a sidewall of each bit line in plan view.

8. A semiconductor device, comprising:

a first line pattern and a second line pattern disposed on a substrate;

a contact plug disposed between the first and second line patterns;

a first air gap disposed between the contact plug and the first line pattern;

a second air gap disposed between the contact plug and the second line pattern;

a conductive landing pad electrically connected to the contact plug and extending from a top end of the contact plug to cover the first air gap; and

an insulating layer disposed on the second air gap, which is not covered by the landing pad,

wherein the first and second air gaps extend in a longitudinal direction of the first and second line patterns; and

wherein the first line pattern comprises a first conductive wire and the second line pattern comprises a second conductive wire.

9. The semiconductor device of claim 8 , wherein a height of the first air gap covered by the landing pad is greater than a height of the second air gap not covered by the landing pad relative to the substrate.

10. The semiconductor device of claim 8 , further comprising:

a first protecting spacer disposed between the first line pattern and the contact plug;

a second protecting spacer disposed between the contact plug and the first protecting spacer,

a third protecting spacer disposed between the second line pattern and the contact plug; and

a fourth protecting spacer disposed between the contact plug and the third protecting spacer,

wherein the first air gap is disposed between the first protecting spacer and the second protecting spacer, and

wherein the second air gap is disposed between the third protecting spacer and the fourth protecting spacer.

11. The semiconductor device of claim 8 , further comprising:

a pair of insulating fences disposed between the first and second line patterns,

wherein the contact plug is disposed between the first and second line patterns and between the pair of insulating fences.

12. The semiconductor device of claim 11 , wherein the first air gap extends between the pair of insulating fences and the first line pattern, and

wherein the second air gap extends between the pair of insulating fences and the second line pattern.

13. A semiconductor device, comprising:

a pair of line patterns disposed on a substrate;

a contact plug disposed between the pair of line patterns;

a spacer structure disposed between the contact plug and each of the line patterns; and

a pair of insulating fences between the pair of line patterns,

wherein the spacer structure comprises:

a first protecting spacer adjacent to each of the line patterns;

a second protecting spacer adjacent to a sidewall of the contact plug; and

an air gap disposed between the first and second protecting spacers, and

wherein the first protecting spacer, the air gap, and the second protecting spacer of the spacer structure have line-shapes extending along a sidewall of each of the line patterns in a plan view,

wherein each of the pair of line patterns comprises a conductive wire,

wherein the contact plug is between the pair of line patterns and between the pair of insulating fences, and

wherein an extending part of the spacer structure is between each of the insulating fences and each of the line patterns.

14. The semiconductor device of claim 13 , further comprising:

a landing pad extending from a top end of the contact plug to cover a part of one of the air gaps; and

an insulating layer disposed on the other one of the air gaps, which is not covered by the landing pad.

15. The semiconductor device of claim 14 , wherein a height of the one of the air gaps covered by the landing pad is greater than a height of the other one of the air gaps not covered by the landing pad relative to the substrate.

16. The semiconductor device of claim 15 , wherein each of the pair of line patterns further comprises a hard mask pattern, the conductive wire and the hard mask pattern being sequentially stacked on the substrate, the hard mask pattern comprising an insulating material, and

wherein the landing pad is in contact with a top surface of the hard mask pattern of a line pattern adjacent to the one of the air gaps.

17. The semiconductor device 15 , further comprising:

a data storage part electrically connected to the landing pad.