Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage

1. A vertical transistor, comprising:

a first III-nitride layer on a second III-nitride layer and comprising a lateral channel;

a polar c-plane interface and nonpolar and/or semipolar interfaces between the first III-nitride layer and the second III-nitride layer;

a drift region connected to the lateral channel, the drift region comprising one or more doped Gallium Nitride layers;

a source contact to the lateral channel;

a drain contact to the drift region; and

one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact, wherein:

the polar interface is between the drift region and one or more gates;

the drift region comprises a current blocking structure;

voltage is predominantly held in a vertical direction in an off-state;

the current is channeled through an aperture in the current-blocking structure after it flows from under the one or more gates, into the drift region in an on-state; and

the one or more gates and/or the current blocking structure:

(i) induce a two dimensional electron gas at one or more sidewalls of the gates and/or of the current blocking structure, and/or

(ii) the current blocking structure comprises different material regions that can provide a compensating charge, wherein the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in the off-state.

2. The device of claim 1 , wherein the current-blocking structure is comprised of trenches filled with insulator and metal to provide the compensating charge.

3. The device of claim 1 , wherein the current-blocking structure is comprised of trenches filled with alternating layers of semiconductor material to provide the compensating charge.

4. The device of claim 1 , wherein the device is a III-nitride device.

5. The device of claim 1 , wherein the current blocking structure:

has the one or more sidewalls adjacent to the current carrying region of the drift region, and

is structured such that the one or more sidewalls reduce resistance to the current's flow in the current carrying drift region.

6. The device of claim 1 , comprising:

a part A bonded to a part B, wherein:

the Part A comprises the one or more gates, the source, and the lateral channel;

the Part B comprises the drift region that carries the current flow via a vertical or sloped two-dimensional electron gas (2-DEG) and along the sidewall; and

the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by the current blocking structure.

7. The device of claim 1 , wherein the drift region is a voltage blocking region that can be fully depleted at voltages lower than a desired breakdown voltage.

8. The device of claim 1 , wherein:

the current blocking structure has one or more dimensions and materials, and

the current-carrying region has one or more dimensions and doping, such that:

an electric field held in the current blocking region is less than its breakdown field in the off-state, and

the current-carrying region becomes fully depleted in the off-state, thus enabling a breakdown voltage of the device.

9. The device of claim 1 , wherein, in the on state, the gates deplete the lateral channel adjacent the gates' sidewalls, so that the current flows predominantly from under the gate to the drift region.

10. The transistor of claim 1 , further comprising:

a plurality of trenches in one or more of the III-nitride layers, wherein the trenches shape the lateral channel; and

one of the gates in each of the trenches.

11. The transistor of claim 10 , wherein the source contact forms metal regions between the gates and mitigates high field regions at the gate edges, ensuring the peak field is in the bulk of the device.

12. The transistor of claim 10 , wherein a polarization induced two dimensional electron gas (2DEG) is formed in regions between the trenches, resulting in the 2DEG which spreads the current efficiently in the drift region to make the full chip area active.

13. The transistor of claim 12 , wherein the channel comprising the 2DEG along the vertical non-polar and/or semipolar interfaces is induced only under forward bias on the gates and the 2DEG on the polar c-plane is always present for all operating conditions.

14. The transistor of claim 13 , wherein the non-polar interface includes an m-plane interface.

15. The transistor of claim 14 , wherein the first III-nitride layer is GaN and the second III-nitride layer is AlGaN.

16. The transistor of claim 1 , further comprising:

a dielectric layer between the gates and the lateral channel, or

the dielectric layer between the gates and the second III-nitride layer and along the interfaces; and

wherein the dielectric provides negligible threshold shift under gate voltages between −10 V and +10V.

17. The transistor of claim 1 , wherein the transistor's electrically active device area is equal to a geometric chip area on which the device is formed and a device having an on resistance of 1 mΩcm 2 has three times smaller chip area for the same R on as a 3 mΩcm 2 device.

18. The transistor of claim 1 , wherein the transistor is a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a vertical Junction Field Effect Transistor.

19. A method of fabricating a vertical transistor, comprising:

depositing a semiconductor structure including a first III-nitride layer on a second III-nitride layer and comprising a lateral channel, wherein:

a polar c-plane interface and nonpolar and/or semipolar interfaces are between the first III-nitride layer and the second III-nitride layer;

the lateral channel is connected to a drift region;

the drift region comprising one or more doped Gallium Nitride layers;

depositing a source contact to the lateral channel;

depositing a drain contact to the drift region;

depositing one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact; and

forming a trench region around a current carrying region of the drift region; and wherein:

the polar interface is between the drift region and one or more gates,

the trench region comprises a current blocking structure comprising different material layers that can provide a compensating charge,

the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in an off-state,

modulation of a current from a source to a drain occurs in the lateral channel,

voltage is predominantly held in a vertical direction in the off-state, and

the current is channeled through an aperture in the current-blocking structure after it flows from under the gates into the drift region in an on-state.