Structure and formation method of fin-like field effect transistor

1. A method for forming a semiconductor device, comprising:

forming a fin structure and another fin structure over a semiconductor substrate;

forming a gate stack over the semiconductor substrate and covering a portion of the fin structure and forming another gate stack over the semiconductor substrate and covering a portion of the another fin structure;

blocking the another fin structure before epitaxially growing source/drain structures and forming a semiconductor protection layer;

epitaxially growing the source/drain structures over the fin structure and adjacent to the gate stack;

forming the semiconductor protection layer over the source/drain structures;

blocking the semiconductor protection layer before another source/drain structure is grown; and

epitaxially growing the another source/drain structure over the another fin structure and adjacent to the another gate stack.

2. The method for forming a semiconductor device as claimed in claim 1 , wherein the semiconductor protection layer is epitaxially grown on the source/drain structures.

3. The method for forming a semiconductor device as claimed in claim 1 , wherein the source/drain structures and the semiconductor protection layer are formed in-situ in a same process chamber.

4. The method for forming a semiconductor device as claimed in claim 1 , further comprising forming another semiconductor protection layer over the another source/drain structure after the blocking of the semiconductor protection layer.

5. The method for forming a semiconductor device as claimed in claim 1 , wherein the semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

6. The method for forming a semiconductor device as claimed in claim 1 , wherein the semiconductor protection layer is not formed under the gate structure.

7. A method for forming a semiconductor device, comprising:

forming a fin structure over a semiconductor substrate;

forming a gate stack over the semiconductor substrate and covering a portion of the fin structure;

after forming the gate stack, forming a source/drain structure on the fin structure adjacent the gate stack; and

depositing a protection layer on the source/drain structure, wherein the protection layer includes an atomic concentration of silicon different than an atomic concentration of silicon in the source/drain structure, and wherein the atomic concentration of silicon is varied during the depositing of the protection layer;

masking the gate stack and the protection layer on the source/drain structure while epitaxially growing another source/drain structure; and

depositing another protection layer over the another source/drain structure, while masking the gate stack and the protection layer.

8. The method of claim 7 , wherein the depositing the protection layer is performed in-situ with the forming of the source/drain structure.

9. The method of claim 7 , wherein the atomic concentration of silicon of the protection layer gradually decreases from a surface of the protection layer towards the source/drain structure.

10. The method of claim 7 , wherein the depositing the protection layer is performed by one or more of a selective epitaxy growth (SEG) process, a CVD process, a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, an ultra-high vacuum CVD (UHV-CVD) process, and a molecular beam epitaxy process.

11. The method of claim 7 , further comprising: annealing after forming the source/drain structure and before depositing the protection layer.

12. The method of claim 7 , wherein during the depositing the protection layer the atomic concentration of silicon is varied by varying a process parameter of an epitaxial deposition.

13. The method of claim 7 , wherein the varying includes increasing the atomic concentration of silicon from an interface with the source/drain structure to a top surface of the protection layer.

14. The method of claim 7 , wherein the forming the source/drain structure includes epitaxially growing a silicon containing feature in a recess of the fin structure.

15. A method of fabricating a semiconductor device structure, comprising:

forming a first fin structure and a second fin structure over a semiconductor substrate;

forming a first gate stack over a portion of the first fin structure and a second gate stack over a portion of the second fin structure;

forming a first source/drain structure adjacent the first gate stack while masking a portion of the second fin structure;

after forming the first source/drain structure, forming a first protection layer over the first source/drain structure;

forming a second source/drain structure adjacent the second gate stack while masking the first source/drain structure; and

after forming the second source/drain structure, forming a second protection layer over the second source/drain structure.

16. The method of claim 15 , wherein the first gate structure is associated with an NMOS device, and the second gate structure is associated with a PMOS device.

17. The method of claim 15 , wherein the forming the first protection layer includes epitaxially growing the first protection layer on the first source/drain structure; and wherein the forming the second protection layer includes epitaxially growing the second protection layer on the second source/drain structure.

18. The method of claim 15 , wherein the forming at least one of the first and second protection layers includes varying an atomic concentration of silicon during deposition.

19. The method of claim 15 , wherein the first protection layer includes an atomic concentration of silicon greater than the first source/drain structure; wherein the second protection layer includes an atomic concentration of silicon greater than the second source/drain structure.

20. The method of claim 7 , wherein the

masking the gate stack and the protection layer includes depositing a dielectric mask layer.