IP Library Granted Patent US 10,340,923
Granted Patent B2
US 10,340,923 · App. 15/354,066 · Granted Jul 2, 2019

Systems and methods for frequency domain calibration and characterization

Inventors: Cho-Ying Lu (Hillsboro, OR); William Yee Li (Portland, OR); Khoa Minh Nguyen (Hillsboro, OR); Ashoke Ravi (Hillsboro, OR); Maneesha Yellepeddi (San Jose, CA); Binta M. Patel (Austin, TX)
Assignee: Intel Corporation
H03L7/085H03L1/00H03L7/08H03L7/091H03L7/0991H03L7/0992H03L2207/50
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Quick Facts
Patent No.
US 10,340,923
App. No.
15/354,066
Granted
Jul 2, 2019
Kind
B2
Abstract

A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.

Claims (21)

1. A system for providing calibration to an oscillator circuit, comprising:

an oscillator circuit configured to generate an output clock signal;

a frequency measurement circuit configured to measure frequencies of the output clock signal and generate a measurement signal representative of the measured frequencies; and

control circuitry configured to generate an adjustment signal based on a comparison of the measurement signal with a reference value,

wherein the frequency measurement circuit includes a first counter and a second counter, where the first counter receives the output clock signal and the second counter receives a reference clock, and wherein the frequency measurement circuit uses the outputs of the first and second counters to generate the measured frequencies.

2. The system of claim 1 , wherein the frequency measurement circuit comprises a counter.

3. The system of claim 1 , further comprising a gain component configured to adjust a gain associated with the oscillator circuit.

4. The system of claim 1 , wherein the adjustment signal includes a phase locked loop gain.

5. The system of claim 4 , wherein the phase locked loop gain and a controlled oscillator gain yield a constant value.

6. A method for performing frequency calibration of an oscillator circuit, comprising:

obtaining frequency measurements of an oscillatory signal by generating a first count associated with the oscillatory signal using a first counter;

determining a deviation of the oscillatory signal based on the obtained frequency measurements by generating a second count using a second counter and employing the first and second counts in determining the deviation; and

generating an adjustment signal based on the determined deviation.

7. The method of claim 6 , wherein determining the deviation of the oscillatory signal comprises identifying frequency shifts due to process, voltage and/or temperature variations.

8. The method of claim 6 , wherein obtaining frequency measurements of the oscillatory signal comprises performing a measurement over a measurement duration associated with the oscillatory signal.

9. The method of claim 6 , wherein determining the deviation of the oscillatory signal comprises identifying resolution shifts due to process, voltage and/or temperature variations.

10. A system for providing calibration to an oscillator circuit, comprising:

an oscillator circuit configured to generate an output clock signal;

a frequency measurement circuit configured to measure frequencies of the output clock signal and generate a measurement signal representative of the measured frequencies; and

control circuitry configured to generate an adjustment signal based on a comparison of the measurement signal with a reference value,

wherein the frequency measurement circuit includes a first counter and a second counter, where the first counter generates a first count associated with the output clock signal and the second counter generates a second count that is employed in ascertaining a deviation of the output clock signal, and wherein the frequency measurement circuit uses the first and second counts of the first and second counters to generate the measured frequencies.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 052916/0308 →
Continuity (3)
Continuation 14857145 · Sep 17, 2015
Continuation 14143116 · Dec 30, 2013
Related Publication 20170070232A1 · Mar 9, 2017