Data processor
A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
1. A processor comprising:
a first-receiver-node for receiving a first-receiver-signal;
a second-receiver-node for receiving a second-receiver-signal;
a first-output-node for coupling to a digital-baseband-processor;
a second-output-node for coupling to the digital-baseband-processor;
a first-active-data-pipe extending between the first-receiver-node and the first-output-node, the first-active-data-pipe comprising:
a first-analogue-to-digital-converter comprising
a first-ADC-input coupled to the first-receiver-node; and
a first-ADC-output coupled to the first-output-node;
wherein the first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node;
a first-reference-node associated with the first-active-data-pipe; and
a configurable-data-pipe extending between the second-receiver-node and the second-output-node, the configurable-data-pipe comprising:
a configurable-pipeline-multiplexer comprising:
a first-MUX-input-node coupled to the second-receiver-node;
a second-MUX-input-node coupled to the first-reference-node; and
a MUX-output-node; and
a second-analogue-to-digital-converter comprising:
a second-ADC-input coupled to the MUX-output-node; and
a second-ADC-output coupled to the second-output-node,
wherein, when the configurable-pipeline-multiplexer is configured to couple the second-MUX-input-node to the MUX-output-node, the second-analogue-to-digital-converter is configured to provide a first-digital-reference-signal to the second-output-node.
2. The processor of claim 1 , wherein the first-reference node is coupled to one of a ground terminal, a reference terminal, a common-mode terminal or a bias voltage terminal.
3. The processor of claim 1 , further comprising a digital baseband processor configured to determine a noise signal based on the first-digital-reference-signal and to subtract the noise signal from the first-digital-signal to provide a noise-cancelled-first-digital-signal to a baseband processor output terminal.
4. The processor of claim 3 , wherein the noise signal is the first-digital-reference-signal.
5. The processor of claim 1 , further comprising a digital baseband processor configured to:
receive the first-digital-reference-signal;
generate control signalling based on the first-digital-reference-signal; and
provide the control signalling to the first-active-data-pipe to configure the first-active-data-pipe.
6. The processor of claim 5 , wherein the digital baseband processor is configured to:
compare the first-digital-reference-signal with a predetermined threshold; and
generate the control signalling based on the result of the comparison.
7. The processor of claim 5 , wherein the digital baseband processor is further configured to receive the first-digital-signal and to generate the control signalling based on the first-digital-signal.
8. The processor of claim 5 , further comprising a digital baseband processor configured to receive signalling representative of a voltage at respective reference nodes and to provide control signalling to the first-active-data-pipe to configure the first-active-data-pipe based on the received signalling.
9. The processor of claim 5 , wherein the first-active-data-pipe further comprises a first-tuner and the digital baseband processor is configured to provide the control signalling to the first-tuner in order to adapt the bandwidth of the first-tuner.
10. The processor of claim 5 , wherein the first-active-data-pipe further comprises a first-pipeline-amplifier and the digital baseband processor is configured to provide the control signalling to the first-pipeline-amplifier in order to adapt a power supplied to the first-pipeline-amplifier.
11. The processor of claim 5 , wherein the first-active-data-pipe further comprises a first-pipeline-amplifier and the digital baseband processor is configured to provide the control signalling to the first-pipeline-amplifier in order to adapt a frequency response to the first-pipeline-amplifier.
12. The processor of claim 5 , wherein the digital baseband processor is configured to:
execute a series of commands according to a predetermined sequence;
detect a spurious-frequency-signal corresponding to a frequency of the predetermined sequence, based on the first-digital-reference-signal; and
modify the predetermined sequence.
13. The processor of claim 1 , further comprising a plurality of reference nodes within the first-active-data-pipe, wherein the configurable-pipeline-multiplexer is configured to selectively couple each of the plurality of reference nodes to the MUX-output node.
14. The processor of claim 1 , further comprising:
a second-active-data-pipe; and
a second-reference-node associated with the second-active-data-pipe,
wherein the configurable-pipeline-multiplexer comprises a third-MUX-input-node coupled to the second-reference-node.
15. An integrated circuit or an electronic device comprising the processor of claim 1 .