Semiconductor substrate with electrically isolating dielectric partition

1. A semiconductor device comprising:

a semiconductor substrate of the semiconductor device comprising a major surface and a backside;

one or more electrical contacts located on the major surface;

a first part of the semiconductor substrate and including an active region of the semiconductor device;

a second part of the semiconductor substrate and including an external sidewall of the semiconductor substrate of the semiconductor device that extends between the major surface and the backside;

a dielectric partition for electrically isolating the first part of the semiconductor substrate from the second part of the semiconductor substrate, wherein the dielectric partition extends through the semiconductor substrate from the major surface to the backside and exposes a portion of the external sidewall to isolate the external sidewall of the second part of the semiconductor substrate from the first part, wherein the dielectric partition extends through adjacent portions of the external sidewall to form an exposed corner of the semiconductor substrate of the semiconductor device, wherein the exposed corner is electrically isolated from the first part of the semiconductor device, and

wherein the semiconductor device is for a chip scale package.

2. The semiconductor device of claim 1 , wherein the first part of the semiconductor substrate includes a first active region of the semiconductor device and wherein the second part of the semiconductor substrate includes a second active region of the semiconductor device.

3. The semiconductor device of claim 1 , wherein the dielectric partition is shaped to define at least one interlocking portion in the semiconductor substrate, wherein the interlocking portion comprises a locking member located on one side of the dielectric partition and an opening located on an opposite side of the dielectric partition, wherein the locking member is received within the opening to inhibit physical separation of the first and second parts of the semiconductor substrate that the dielectric partition electrically isolates.

4. The semiconductor device of claim 3 , wherein the locking member of the at least one interlocking portion includes a neck portion and a head portion, wherein the opening includes a mouth portion within which the neck portion of the locking member is received, and wherein the head portion of the locking member is at least as wide as the mouth portion of the opening when viewed from above the major surface, to prevent removal of the head portion from the opening.

5. The semiconductor device of claim 4 , wherein the locking member is trapezoidal in shape when viewed from above the major surface.

6. The semiconductor device of claim 3 , wherein edges of the locking member are curved when viewed from above the major surface.

7. The semiconductor device of claim 3 , wherein the dielectric partition includes a plurality of the interlocking portions.

8. The semiconductor device of claim 1 , wherein the semiconductor substrate includes at least one further part, and wherein the first part, the second part and each further part of the semiconductor substrate are electrically isolated from neighboring parts by one or more of the dielectric partitions.

9. A chip scale package comprising the semiconductor device of claim 1 .

10. A chip-scale package (CSP) semiconductor device comprising:

a semiconductor substrate of the CSP semiconductor device comprising a mayor surface and a backside;

one or more electrical contacts located on the major surface:

a first part of the semiconductor substrate and including an active region of the CSP semiconductor device;

a second part of the semiconductor substrate and including an external sidewall of the semiconductor substrate of the CSP semiconductor device that extends between the major surface and the backside; and

a plurality of dielectric partitions comprising

a dielectric partition for electrically isolating the first part of the semiconductor substrate from the second part of the semiconductor substrate, wherein the dielectric partition extends through the semiconductor substrate from the major surface to the backside and exposes a portion of the external sidewall to isolate the external sidewall of the second part of the semiconductor substrate from the first part and

at least one further dielectric partition,

wherein at least some dielectric partitions of the plurality of dielectric partitions of the CSP semiconductor device intersect,

wherein the first part of the semiconductor substrate is electrically isolated from the second part of the semiconductor substrate.

11. A method of making a semiconductor device, the method comprising:

providing a wafer having a major surface and a backside;

forming a trench that extends from the major surface at least partially through the wafer;

at least partially filling the trench with dielectric;

forming a plurality of electrical contacts on the major surface;

removing material from the backside of the wafer at least until a bottom of the trench is exposed; and

singulating the wafer to form a plurality of semiconductor substrates, wherein each of the semiconductor substrates includes one or more of the electrical contacts, wherein at least one semiconductor substrate of the plurality of semiconductor substrates includes a dielectric partition formed from the dielectric filled trench, wherein the dielectric partition electrically isolates a first part of the semiconductor substrate from a second part of the semiconductor substrate,

wherein the first part of the semiconductor substrate includes an active region of the semiconductor device and wherein the second part of the substrate includes an external sidewall of the semiconductor substrate that extends between a major surface and a backside of the semiconductor substrate corresponding to the major surface and backside of the wafer, and

wherein the dielectric partition extends through the semiconductor substrate from the major surface to the backside and exposes a portion of the external sidewall to isolate the external sidewall of the second part of the semiconductor substrate from the first parts wherein the dielectric partition extends through adjacent portions of the external sidewall to form an exposed corner of the semiconductor substrate of the semiconductor device, wherein the exposed corner is electrically isolated from the first part of the semiconductor device, and

wherein the semiconductor device is for a chip scale package.

12. The method of claim 11 , wherein the dielectric partition is shaped to define at least one interlocking portion in the semiconductor substrate, wherein the interlocking portion comprises a locking member located on one side of the dielectric partition and an opening located on an opposite side of the dielectric partition, wherein the locking member is received within the opening to inhibit physical separation of the parts of the semiconductor substrate that the dielectric partition electrically isolates.