Manufacturing method of memory device
The invention provides a memory device. The memory device includes a substrate, a plurality of first wires, a plurality of etch-stop layers, a dielectric layer, and a plurality of vias. The substrate has a plurality of first regions and a plurality of second regions arranged in a staggered manner along a first direction. The first wires are embedded in the substrate and extended along the first direction. The first wires include a conductive layer and a cap layer located on the conductive layer, and the upper surface of the cap layer has a groove. The etch-stop layers are located on the cap layer and filled in the groove. The dielectric layer is located on the substrate and has a plurality of via openings in the first regions. The via openings expose the substrate and the etch-stop layer. The vias are filled in the via openings and electrically connected to the substrate. The invention further provides a manufacturing method of a memory device.
1. A manufacturing method of a memory device, comprising:
providing a substrate, wherein the substrate has a plurality of first regions and a plurality of second regions, and the first regions and the second regions are arranged in a staggered manner along a first direction;
forming a plurality of first wires in the substrate, wherein the first wires are extended along the first direction, and the first wires comprise a conductive layer and a cap layer located on the conductive layer;
removing a portion of the cap layer to form a groove in an upper surface of the cap layer, such that a portion of a sidewall of the substrate is exposed by the groove;
forming an etch-stop layer, wherein the etch-stop layer at least covers the cap layer and is filled in the groove;
forming a dielectric layer, wherein the dielectric layer in the first regions covers the first wires and the substrate;
forming a plurality of openings in the dielectric layer in the first regions, wherein the openings expose an upper surface of the etch-stop layer;
etching the openings to form a plurality of via openings, wherein the via openings expose an upper surface of the substrate and the groove; and
forming a plurality of vias, wherein the vias are filled in the via openings and each of the vias is electrically contacted with the portion of the sidewall of the substrate exposed by the groove.
2. The manufacturing method of the memory device of claim 1 , wherein a method of forming the etch-stop layer comprises:
forming a first etch-stop layer, wherein the first etch-stop layer at least covers the cap layer and is filled in the groove; and
forming a second etch-stop layer, wherein the second etch-stop layer at least covers the first etch-stop layer and the cap layer.
3. The manufacturing method of the memory device of claim 1 , further comprising:
forming a plurality of first isolation structures in the substrate before a portion of the cap layer is removed, wherein the first wires are respectively located at two sides of the first isolation structures; and
forming a plurality of second isolation structures in the substrate before a portion of the cap layer is removed, wherein the second isolation structures are respectively located in the substrate of the first regions between two adjacent first isolation structures.
4. The manufacturing method of the memory device of claim 1 , further comprising forming a plurality of second wires in the second regions after the etch-stop layer is formed, wherein the second wires are extended along a second direction and cover the etch-stop layer and the substrate, and the first direction is different from the second direction.