Low power and low latency GPU coprocessor for persistent computing

1. A system comprising:

a regular queue;

a persistent queue, wherein the persistent queue is configured to store data for execution of a persistent compute kernel;

a graphics processing unit (GPU);

a GPU coprocessor; and

a host processor configured to:

initialize the GPU coprocessor with the persistent compute kernel which is to be executed indefinitely by the GPU coprocessor, wherein subsequent to the persistent computer kernel being initialized by the host processor, the GPU coprocessor executes the persistent compute kernel until the host processor notifies the GPU coprocessor to stop executing the persistent compute kernel;

send, to the regular queue, input data for processing by the GPU; and

send, to the persistent queue, messages mapped to sub-tasks targeting the GPU coprocessor for execution;

wherein the GPU coprocessor is configured to:

monitor the persistent queue;

in response to detecting a message in the persistent queue:

identify a first sub-task for execution by the GPU coprocessor; and

schedule the first sub-task for execution by the GPU coprocessor.

2. The system as recited in claim 1 , wherein the GPU coprocessor is further configured to:

perform a lookup of an event table for the first message responsive to detecting the first message;

map the first message to a first event using the event table;

schedule the first sub-task for execution by the GPU coprocessor responsive to mapping the first message to the first event; and

continue to service subsequent messages when computing resources of the GPU coprocessor are available.

3. The system as recited in claim 2 , wherein the GPU coprocessor is further configured to:

detect a second message in the queue;

map the second message to a second event using the event table;

schedule a second task for performing a matrix transpose operation on a first matrix responsive to mapping the second message to the second event;

utilize a crossbar to rotate data items in the first matrix to create a second matrix;

utilize a plurality of biased indexing operations to rearrange data items in the second matrix to create a third matrix; and

utilize the crossbar to rotate data items in the third matrix to create a fourth matrix, wherein the fourth matrix is a transposed version of the first matrix.

4. The system as recited in claim 1 , wherein the GPU coprocessor comprises:

a single instruction, multiple data (SIMD) unit comprising a plurality of arithmetic logic units (ALUs);

a plurality of register files coupled to the plurality of ALUs; and

a crossbar; and

wherein the GPU coprocessor is further configured to:

convey multiple operands to the SIMD unit in a single clock cycle; and

issue more than one instruction in the single clock cycle.

5. The system as recited in claim 4 , wherein the GPU coprocessor further comprises:

a first vector general purpose register (VGPR) file with one read port and one write port of the plurality of register files; and

a second VGPR file with multiple read ports and one write port of the plurality of register files; and

a biased index access block; and

wherein the first VGPR file is a multi-bank array, and wherein the GPU coprocessor is configured to access different word lines of separate banks of the first VGPR file in a single clock cycle using the biased index access block.

6. The system as recited in claim 1 , wherein:

the host processor schedules graphics processing tasks on the GPU for a video stream; and

the host processor programs the GPU coprocessor to perform audio processing tasks for the video stream.

7. The system as recited in claim 1 , wherein:

the GPU coprocessor further comprises a scalar unit and a vector unit;

the scalar unit is configured to:

monitor the queue for messages;

schedule sub-tasks for execution on the vector unit.

8. A method comprising:

initializing, by a host processor, a GPU coprocessor with a persistent compute kernel which is to be executed indefinitely by the GPU coprocessor, wherein subsequent to the persistent computer kernel being initialized by the host processor, the GPU coprocessor executes the persistent compute kernel until the host processor notifies the GPU coprocessor to stop executing the persistent compute kernel;

sending, to a regular queue, input data for processing by a GPU from the host processor;

sending messages mapped to sub-tasks targeting the GPU coprocessor for execution from the host processor to a persistent queue, wherein the persistent queue is configured to store data for execution of a persistent compute kernel;

monitoring, by the GPU coprocessor, the persistent queue;

in response to detecting a message in the persistent queue:

identifying a first sub-task for execution by the GPU coprocessor; and

scheduling, by the GPU coprocessor, the first sub-task for execution by the GPU coprocessor.

9. The method as recited in claim 8 , further comprising:

performing a lookup of an event table for the first message responsive to detecting the first message;

mapping the first message to a first event using the event table;

scheduling the first sub-task for execution by the GPU coprocessor responsive to mapping the first message to the first event; and

continuing to service subsequent messages when computing resources of the GPU coprocessor are available.

10. The method as recited in claim 9 , further comprising:

detecting a second message in the queue;

mapping the second message to a second event using the event table;

scheduling a second task for performing a matrix transpose operation on a first matrix responsive to mapping the second message to the second event;

utilizing a crossbar to rotate data items in the first matrix to create a second matrix;

utilizing a plurality of biased indexing operations to rearrange data items in the second matrix to create a third matrix; and

utilizing the crossbar to rotate data items in the third matrix to create a fourth matrix, wherein the fourth matrix is a transposed version of the first matrix.

11. The method as recited in claim 8 , wherein the GPU coprocessor comprises:

a single instruction, multiple data (SIMD) unit comprising a plurality of arithmetic logic units (ALUs);

a plurality of register files coupled to the plurality of ALUs; and

a crossbar; and

wherein the method further comprising:

conveying multiple operands from the second VGPR file to the SIMD unit in a single clock cycle; and

issuing more than one instruction in the single clock cycle.

12. The method as recited in claim 11 , wherein the GPU coprocessor further comprises:

a first vector general purpose register (VGPR) file with one read port and one write port of the plurality of register files; and

a second VGPR file with multiple read ports and one write port of the plurality of register files; and

a biased index access block; and

wherein the first VGPR file is a multi-bank array, and wherein the method further comprises accessing different word lines of separate banks of the first VGPR file in a single clock cycle using the biased index access block.

13. The method as recited in claim 8 , wherein the method further comprises:

scheduling video processing tasks on the GPU for a multimedia process; and

programming the GPU coprocessor to perform audio processing tasks for the multimedia process.

14. The method as recited in claim 8 , wherein:

the GPU coprocessor further comprises a scalar unit and a vector unit;

wherein the method further comprises:

monitoring, by the scalar unit, the queue for messages;

scheduling, by the scalar unit, sub-tasks for execution on the vector unit.

15. A graphics processing unit (GPU) coprocessor comprising:

a scalar unit; and

a vector unit;

wherein the scalar unit is configured to:

monitor a persistent queue, wherein the persistent queue is configured to store data for execution of a persistent compute kernel;

execute indefinitely the persistent compute kernel, after being initialized by an external host processor, wherein subsequent to the persistent computer kernel being initialized by the host processor, the GPU coprocessor executes the persistent compute kernel until the host processor notifies the GPU coprocessor to stop executing the persistent compute kernel; and

in response to detecting a message in the persistent queue:

identify a first sub-task for execution by the GPU coprocessor; and

schedule the first sub-task for execution on the vector unit.

16. The GPU coprocessor as recited in claim 15 , wherein the GPU coprocessor is configured to:

perform a lookup of an event table for the first message responsive to detecting the first message;

map the first message to a first event using the event table;

schedule the first sub-task for execution on the vector unit responsive to mapping the first message to the first event; and

continue to service subsequent messages when the vector unit is available.

17. The GPU coprocessor as recited in claim 16 , wherein the GPU coprocessor is further configured to:

detect a second message in the queue;

map the second message to a second event using the event table;

schedule a second task for performing a matrix transpose operation on a first matrix responsive to mapping the second message to the second event; and

utilize a crossbar to rotate data items in the first matrix to create a second matrix.

18. The GPU coprocessor as recited in claim 17 , wherein the GPU coprocessor is further configured to:

utilize a plurality of biased indexing operations to rearrange data items in the second matrix to create a third matrix; and

utilize the crossbar to rotate data items in the third matrix to create a fourth matrix, wherein the fourth matrix is a transposed version of the first matrix.

19. The GPU coprocessor as recited in claim 15 , wherein the GPU coprocessor comprises:

a single instruction, multiple data (SIMD) unit comprising a plurality of arithmetic logic units (ALUs);

a plurality of register files coupled to the plurality of ALUs; and

a crossbar; and

wherein the GPU coprocessor further configured to:

convey multiple operands from the second VGPR file to the vector unit in a single clock cycle; and

issue more than one instruction in the single clock cycle.

20. The GPU coprocessor as recited in claim 19 , wherein the GPU coprocessor further comprises:

a first vector general purpose register (VGPR) file with one read port and one write port of the plurality of register files; and

a second VGPR file with multiple read ports and one write port of the plurality of register files; and

a biased index access block; and

wherein the first VGPR file is a multi-bank array, and wherein the GPU coprocessor is configured to access different word lines of separate banks of the first VGPR file in a single clock cycle using the biased index access block.