Interconnect via with grown graphitic material
An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.
1. An integrated circuit, comprising:
a substrate comprising a semiconductor material;
an active component in the substrate;
an interconnect region above the substrate;
a first electrically conductive member;
a second electrically conductive member in the interconnect region above the first electrically conductive member; and
a graphitic via in the interconnect region, wherein:
the graphitic via comprises a cohered nanoparticle film on at least one sidewall of the graphitic via;
the cohered nanoparticle film comprises primarily nanoparticles;
the nanoparticles comprise a metal suitable for catalysis of graphitic material;
the graphitic via comprises a layer of graphitic material on the cohered nanoparticle film;
the graphitic via is electrically conductive;
the cohered nanoparticle film makes electrical contact to the first electrically conductive member; and
the second electrically conductive member makes electrical contact to: the cohered nanoparticle film; and the layer of graphitic material.
2. The integrated circuit of claim 1 , wherein the metal suitable for catalysis of graphitic material is selected from the group consisting of copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, and gold.
3. The integrated circuit of claim 1 , wherein the graphitic material comprises a material selected from the group consisting of graphite, graphitic carbon, graphene, and/or carbon nanotubes.
4. The integrated circuit of claim 1 , wherein the first electrically conductive member is a node of the active component, and the second electrically conductive member is an interconnect in the interconnect region.
5. The integrated circuit of claim 1 , wherein the first electrically conductive member is a first interconnect in the interconnect region, and the second electrically conductive member is a second interconnect in the interconnect region.
6. The integrated circuit of claim 1 , wherein the first electrically conductive member is a lower winding of an inductor in the interconnect region, and the second electrically conductive member is an upper winding of the inductor.
7. The integrated circuit of claim 1 , wherein a length of the graphitic via is at least two times greater than a width of the graphitic via.
8. The integrated circuit of claim 1 , wherein the graphitic via is a first graphitic via having a first width, the first graphitic via being in a dielectric layer of the interconnect region, and the integrated circuit further comprises a second graphitic via in the dielectric layer, the second graphitic via having a second width at least two times greater than the first width.
9. The integrated circuit of claim 1 , wherein the cohered nanoparticle film is a first cohered nanoparticle film, and the integrated circuit further comprises a thermal routing component comprising a second cohered nanoparticle film, the thermal routing component being selected from the group consisting of a deep trench thermal routing structure, a top level thermal conductivity structure, a high thermal conductivity lateral structure, a high thermal conductivity via, and a high thermal conductivity through-package conduit; wherein:
the deep trench thermal routing structure is in the substrate and extends to a boundary between the substrate and the interconnect region;
the top level thermal conductivity structure is above the interconnect region;
the high thermal conductivity lateral structure is in the interconnect region;
the high thermal conductivity via is in the interconnect region; and
the high thermal conductivity through-package conduit is through an encapsulation material over the integrated circuit and extends to the integrated circuit.
10. The integrated circuit of claim 1 , wherein the cohered nanoparticle film is essentially free of an organic binder material.
11. The integrated circuit of claim 1 , wherein the graphitic material includes multiple layers of graphene.
12. The integrated circuit of claim 1 , wherein adjacent nanoparticles are cohered to each other.
13. An integrated circuit, comprising:
first and second dielectric layers located over a semiconductor substrate;
a first metal interconnect line located within a first dielectric layer located over the substrate;
a second metal interconnect line located within a second dielectric layer located over the substrate; and
a conductive via comprising a graphitic material located within a third dielectric layer and between the first and second interconnects, wherein the via further comprises a nanoparticle film located between the graphitic material and the first metal interconnect and between the graphitic material and the third dielectric layer.
14. The integrated circuit of claim 13 , wherein the nanoparticle film comprises a metal selected from the group consisting of copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, and gold.
15. The integrated circuit of claim 13 , wherein the graphitic material comprises a plurality of graphene layers.
16. The integrated circuit of claim 13 , wherein adjacent nanoparticles are cohered to each other.