IP Library Granted Patent US 10,237,156
Granted Patent B2
US 10,237,156 · App. 15/361,528 · Granted Mar 19, 2019

Low-complexity measurement of packet traversal time in network element

Inventors: Oded Belfer (Tel Aviv, IL); George Elias (Tel Aviv, IL); Gil Levy (Hod Hasharon, IL)
Assignee: Mellanox Technologies TLV Ltd.
H04L43/0894H04L43/106
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Quick Facts
Patent No.
US 10,237,156
App. No.
15/361,528
Granted
Mar 19, 2019
Kind
B2
Abstract

A network element includes multiple interfaces and circuitry. The interfaces are configured to connect to a communication system. The circuitry is configured to receive via an ingress interface a packet that includes an Error Detection Code (EDC) field including an input EDC value, to determine an input timestamp indicative of a time-of-arrival of the received packet at the network element, and overwrite at least part of the input EDC value in the EDC field of the packet with the input timestamp, to estimate for the packet a traversal latency between reception at the ingress interface and transmission via a selected egress interface, based at least on the input timestamp, and to produce a deliverable version of the packet by writing an output EDC value to the EDC field, and send the deliverable version of the packet via the selected egress interface.

Claims (26)

1. A network element, comprising:

multiple interfaces, which are configured to connect to a communication system; and

circuitry, which is configured to:

receive via an ingress interface a packet that comprises an Error Detection Code (EDC) field comprising an input EDC value;

determine an input timestamp indicative of a time-of-arrival of the received packet at the network element, and write the input timestamp to replace at least part of the input EDC value in the EDC field of the packet;

estimate for the packet a traversal latency between reception at the ingress interface and transmission via a selected egress interface, based at least on the input timestamp;

calculate an output EDC value over one or more fields of the packet, excluding the EDC field in which the timestamp was written; and

produce a deliverable version of the packet by writing the calculated output EDC value to the EDC field, instead of the timestamp, and send the deliverable version of the packet via the selected egress interface.

2. The network element according to claim 1 , wherein the network element comprises a switch in an Infiniband network, wherein the EDC field comprises a Variant Cyclic Redundancy Check (VCRC) field, and wherein the circuitry is configured to evaluate an EDC value over the one or more fields of the received packet, and to produce the output EDC value over the packet to be sent, in accordance with an Infiniband specification.

3. The network element according to claim 1 , wherein the input timestamp requires a storage space larger than the EDC field, and wherein the circuitry is configured to write the input timestamp to replace the at least part of the input EDC value, by allocating for the received packet a storage space larger than required for storing the received packet with the EDC field.

4. The network element according to claim 1 , wherein the circuitry is configured to estimate the traversal latency, by determining an output timestamp indicative of a time-of-departure of the packet to the communication system via the selected egress interface, and calculating a difference between the output timestamp and the input timestamp.

5. The network element according to claim 1 , wherein the circuitry is configured to produce the deliverable version of the packet by changing a value of a given field in the packet, and to evaluate the output EDC value after the given field has been changed.

6. The network element according to claim 5 , wherein the given field comprises a Virtual lane (VL) field in accordance with an Infiniband specification.

7. The network element according to claim 1 , wherein the circuitry is configured to derive a histogram of traversal latencies from multiple packets received via ingress interfaces of the network element, and to update the histogram using the estimated traversal latency of the packet.

8. A method, comprising:

receiving via an ingress interface of a network element that comprises multiple interfaces for connecting to a communication system, a packet that comprises an Error Detection Check (EDC) field comprising an input EDC value;

determining an input timestamp indicative of a time-of-arrival of the received packet at the network element, and writing the input timestamp to replace at least part of the input EDC value in the EDC field of the packet;

estimating for the packet a traversal latency between reception at the ingress interface and transmission via a selected egress interface, based at least on the input timestamp;

calculating an output EDC value over one or more fields of the packet, excluding the EDC field in which the timestamp was written; and

producing a deliverable version of the packet by writing the calculated output EDC value to the EDC field, instead of the timestamp, and sending the deliverable version of the packet via the selected egress interface.

9. The method according to claim 8 , wherein the network element comprises a switch in an Infiniband network, wherein the EDC field comprises a Variant Cyclic Redundancy Check (VCRC) field, and further comprising evaluating an EDC value over the one or more fields of the received packet, and producing the output EDC value over the packet to be sent, in accordance with an Infiniband specification.

10. The method according to claim 8 , wherein the input timestamp requires a storage space larger than the EDC field, and wherein writing the input timestamp to replace the at least part of the input EDC value comprises allocating for the received packet a storage space larger than required for storing the received packet with the EDC field.

11. The method according to claim 8 , wherein estimating the traversal latency comprises determining an output timestamp indicative of a time-of-departure of the packet to the communication system via the selected egress interface, and calculating a difference between the output timestamp and the input timestamp.

12. The method according to claim 8 , wherein producing the deliverable version of the packet comprises changing a value of a given field in the packet, and evaluating the output EDC value after the given field has been changed.

13. The method according to claim 12 , wherein the given field comprises a Virtual lane (VL) field in accordance with an Infiniband specification.

14. The method according to claim 8 , and comprising deriving a histogram of traversal latencies from multiple packets received via ingress interfaces of the network element, and updating the histogram using the estimated traversal latency of the packet.

Assignments (4)
MERGER Recorded Dec 15, 2021
From: MELLANOX TECHNOLOGIES TLV LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 058517/0564 →
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 42962/0859 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Reel/Frame 046551/0459 →
SECURITY INTEREST Recorded Jun 23, 2017
From: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 042962/0859 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2016
From: BELFER, ODED; ELIAS, GEORGE; LEVY, GIL
To: MELLANOX TECHNOLOGIES TLV LTD.
Reel/Frame 040423/0284 →
Continuity (1)
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