Patent Assignment
Reel/Frame 042962/0859
Security Interest
Recorded: 2017-06-23
Pages: 21
Assignors
MELLANOX TECHNOLOGIES, LTD.
Executed: 2017-06-19
MELLANOX TECHNOLOGIES TLV LTD.
Executed: 2017-06-19
MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Executed: 2017-06-19
Assignee
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
10 S. DEARBORN, 7TH FLOOR, CHICAGO, ILLINOIS, 60603
Covered Properties
(181)
Optical Source with Monitor
Patent:
6,111,903 →
Application:
09/103,723 →
Field Modulated Vertical Cavity Surface-Emitting Laser with Internal Optical Pumping
Patent:
6,285,704 →
Application:
09/114,142 →
High Powered Laser Diode
Patent:
6,163,556 →
Application:
09/114,143 →
Vertical Cavity Surface Emitting Laser
Patent:
6,356,573 →
Application:
09/235,302 →
Vcsel with Monitor Emission Through High Reflectivity Mirror
Patent:
6,879,611 →
Application:
09/438,955 →
Top contact vcsel with monitor
Patent:
6,368,890 →
Application:
09/506,895 →
Deterministic Search Algorithm
Patent:
6,625,612 →
Application:
09/593,397 →
High-Performance Network Processor
Patent:
6,778,534 →
Application:
09/609,221 →
Look-Ahead Tree Structure
Patent:
6,532,457 →
Application:
09/616,877 →
Method for the Controlled Oxidiation of Materials
Patent:
6,555,407 →
Application:
09/693,233 →
Wildcards in Radix- Search Tree Structures
Pre-Fusion Oxidized and Wafer-Bonded Vertical Cavity Laser
Top Contact Vcsel with Monitor
Transverse Mode and Polarization Control of Surface Emitting Lasers Through the Formation of a Dielectric Stack
Photonic Device with Monitor
Flow Control in a Parallel Processing Environment
Patent:
8,018,849 →
Application:
11/313,895 →
Buffering Data in a Parallel Processing Environment
Patent:
7,668,979 →
Application:
11/313,900 →
Managing Data Flows in a Parallel Processing Environment
Patent:
7,814,242 →
Application:
11/314,254 →
Managing Buffer Storage in a Parallel Processing Environment
Patent:
7,853,774 →
Application:
11/314,270 →
Transferring Data in a Parallel Processing Environment
Patent:
7,461,236 →
Application:
11/314,861 →
Managing Memory in a Parallel Processing Environment
Patent:
7,624,248 →
Application:
11/404,187 →
Mapping Memory in a Parallel Processing Environment
Patent:
7,620,791 →
Application:
11/404,207 →
Directing Data in a Parallel Processing Environment
Patent:
7,793,074 →
Application:
11/404,281 →
Coupling Integrated Circuits in a Parallel Processing Environment
Patent:
7,539,845 →
Application:
11/404,409 →
Protection in a Parallel Processing Environment Using Access Information Associated with Each Switch to Prevent Data from Being Forwarded Outside a Plurality of Tiles
Patent:
7,774,579 →
Application:
11/404,461 →
Managing Cache Memory in a Parallel Processing Environment
Patent:
7,882,307 →
Application:
11/404,641 →
Managing Set Associative Cache Memory According to Entry Type
Patent:
7,461,210 →
Application:
11/404,654 →
Managing Memory Access in a Parallel Processing Environment
Patent:
7,805,577 →
Application:
11/404,655 →
Coupling Data in a Parallel Processing Environment
Patent:
7,636,835 →
Application:
11/404,658 →
Managing Data in a Parallel Processing Environment
Patent:
7,577,820 →
Application:
11/404,958 →
Pattern Matching in a Multiprocessor Environment with Finite State Automaton Transitions Based on an Order of Vectors in a State Transition Table
Patent:
7,805,392 →
Application:
11/564,694 →
Programming in a Multiprocessor Environment
Patent:
9,009,660 →
Application:
11/564,723 →
Pattern Matching
Patent:
7,877,401 →
Application:
11/753,315 →
Packet Processing in a Parallel Processing Environment
Patent:
8,194,690 →
Application:
11/753,325 →
Caching in Multicore and Multiprocessor Architectures
Patent:
7,853,752 →
Application:
11/754,016 →
Caching in Multicore and Multiprocessor Architectures
Patent:
7,853,754 →
Application:
11/754,062 →
Caching in Multicore and Multiprocessor Architectures
Patent:
7,805,575 →
Application:
11/754,118 →
Caching in Multicore and Multiprocessor Architectures
Patent:
7,853,755 →
Application:
11/754,162 →
Compiling Code for Parallel Processing Architectures Based on Control Flow
Patent:
8,250,555 →
Application:
12/028,002 →
Distributing Parallelism for Parallel Processing Architectures
Patent:
8,250,556 →
Application:
12/028,003 →
Communication Scheduling for Parallel Processing Architectures
Patent:
8,291,400 →
Application:
12/028,005 →
Memory Access Assignment for Parallel Processing Architectures
Patent:
8,181,168 →
Application:
12/028,007 →
Coupling Data for Interrupt Processing in a Parallel Processing Environment
Patent:
8,190,855 →
Application:
12/036,918 →
Managing Data Forwarded Between Processors in a Parallel Processing Environment Based on Operations Associated with Instructions Issued by the Processors
Patent:
7,734,894 →
Application:
12/110,871 →
Managing Data Provided to Switches in a Parallel Processing Environment
Patent:
8,127,111 →
Application:
12/110,956 →
Configuring Routing in Mesh Networks
Patent:
8,050,256 →
Application:
12/169,436 →
Configuring Routing in Mesh Networks
Patent:
8,045,546 →
Application:
12/169,442 →
Configuring Routing in Mesh Networks
Patent:
8,151,088 →
Application:
12/169,456 →
Electric Nanodevice and Method of Manufacturing Same
Managing Shared Resource in an Operating System by Distributing Reference to Object and Setting Protection Levels
Patent:
8,799,914 →
Application:
12/885,957 →
Low-Overhead Operating Systems
Patent:
8,327,187 →
Application:
12/885,978 →
Managing Cache Coherence
Patent:
8,392,661 →
Application:
12/885,994 →
Supporting Secondary Atomic Operations Using Primary Atomic Operations
Patent:
8,549,249 →
Application:
12/886,013 →
Managing Memory Requests Based on Priority
Patent:
8,886,899 →
Application:
12/886,050 →
Memory Controller Load Balancing with Configurable Striping Domains
Patent:
9,063,825 →
Application:
12/886,136 →
Route Prediction in Packet Switched Networks
Patent:
9,135,215 →
Application:
12/886,163 →
Low Latency Dynamic Route Selection
Patent:
8,934,347 →
Application:
12/886,346 →
Managing Cache Access and Streaming Data
Patent:
9,213,652 →
Application:
12/886,365 →
Condensed Router Headers with Low Latency Output Port Calculation
Patent:
8,572,353 →
Application:
12/886,366 →
Managing Home Cache Assignment
Patent:
8,539,155 →
Application:
12/886,372 →
Managing Cache Coherence
Patent:
8,521,963 →
Application:
12/886,376 →
Configurable Device Interfaces
Patent:
8,799,624 →
Application:
12/886,382 →
Memory-Mapped Data Transfers
Patent:
8,612,711 →
Application:
12/886,386 →
Pattern Matching in a Multiprocessor Environment
Patent:
8,065,259 →
Application:
12/890,996 →
Caching in Multicore and Multiprocessor Architectures
Patent:
8,112,581 →
Application:
12/958,920 →
Caching in Multicore and Multiprocessor Architectures
Patent:
7,987,321 →
Application:
12/966,686 →
Pattern Matching
Patent:
8,620,940 →
Application:
12/977,565 →
Managing Cache Memory in a Parallel Processing Environment
Patent:
8,200,901 →
Application:
12/983,368 →
Pattern Matching in a Multiprocessor Environment
Patent:
8,086,554 →
Application:
13/188,580 →
Caching in Multicore and Multiprocessor Architectures
Patent:
8,234,451 →
Application:
13/190,035 →
Transferring and Storing Data in Multicore and Multiprocessor Architectures
Patent:
8,677,081 →
Application:
13/211,065 →
Flow Control in a Parallel Processing Environment
Patent:
8,635,378 →
Application:
13/229,294 →
Configuring Routing in Mesh Networks
Patent:
8,737,392 →
Application:
13/278,663 →
Configuring Routing in Mesh Networks
Patent:
9,384,165 →
Application:
13/278,676 →
Computing in Parallel Processing Environments
Patent:
8,738,860 →
Application:
13/280,927 →
Packet Processing in a Parallel Processing Environment
High Speed Lasing Device
Managing Cache Memory in a Parallel Processing Environment
Patent:
8,631,205 →
Application:
13/491,413 →
Caching in Multicore and Multiprocessor Architectures
Patent:
8,560,780 →
Application:
13/553,884 →
Compiling Code for Parallel Processing Architectures Based on Control Flow
Patent:
8,949,806 →
Application:
13/588,141 →
High Performance, Scalable Multi Chip Interconnect
Caching in Multicore and Multiprocessor Architectures
Patent:
9,514,050 →
Application:
14/047,128 →
Managing Cache Memory in a Parallel Processing Environment
Patent:
9,298,618 →
Application:
14/154,277 →
Flow Control In A Parallel Processing Environment
Patent:
9,329,798 →
Application:
14/159,608 →
Cache Coherency in Multiprocessor System
Patent:
11,151,033 →
Application:
14/208,405 →
Global Socket to Socket Cache Coherence Architecture
Patent:
10,339,059 →
Application:
14/246,213 →
Computing in Parallel Processing Environments
Patent:
10,095,543 →
Application:
14/286,000 →
Managing Shared Resources In An Operating System
Patent:
10,067,796 →
Application:
14/450,476 →
Configurable Device Interfaces
Patent:
9,858,200 →
Application:
14/450,527 →
Multi-Core Processor Using Three Dimensional Integration
Patent:
9,886,275 →
Application:
14/508,027 →
Low Latency Dynamic Route Selection
Patent:
9,507,745 →
Application:
14/594,299 →
Computing In Parallel Processing Environments
Patent:
10,078,613 →
Application:
14/636,296 →
Programming In A Multiprocessor Environment
Patent:
9,934,010 →
Application:
14/675,935 →
Memory Controller Load Balancing With Configurable Striping Domains
Patent:
9,753,854 →
Application:
14/747,044 →
Route Prediction In Packet Switched Networks
Patent:
9,479,431 →
Application:
14/854,286 →
Managing Cache Access and Streaming Data
Patent:
10,210,092 →
Application:
14/967,665 →
Reducing Power Requirements for Optical Links
Application:
15/048,924 →
Publication:
US 2016/0173203
Unicast Forwarding of Adaptive-Routing Notifications
Remote host management over a network
Control of persistent memory via a computer bus
Flexible buffer allocation in a network switch
Optoelectronic Transducer with Integrally Mounted Thermoelectric Cooler
Temperature Control of Components on an Optical Device
Flexible Application of Congestion Control Measures
Systems and Methods for Distributed Storage of Data Across Multiple Hash Tables
Using a Single Work Item to Send Multiple Messages
Optimizing buffer allocation for network flow control
Redundant and Reconfigurable Optical Transceiver
Patent:
9,692,511 →
Application:
15/082,313 →
Managing Cache Memory In A Parallel Processing Environment
Patent:
9,639,487 →
Application:
15/083,408 →
Single Double Cuckoo Hash
Facilitating Communication of Data Packets Using Credit-Based Flow Control
Electro-Optic Transceiver Module with Wavelength Compensation
Control of communication network performance by varying active optical cable parameters
Compact optical fiber splitters
Application:
15/137,048 →
Publication:
US 2016/0238789
Flow Control In A Parallel Processing Environment
Patent:
10,002,096 →
Application:
15/143,754 →
Packet Steering
Network-based computational accelerator
Efficient transport flow processing on an accelerator
Silicon Photonics Connector
Forwarding of adaptive routing notifications
Host bus access by add-on devices via a network interface controller
Efficient use of buffer space in a network switch
Temperature Control of a Component on an Optical Device
End-To-End Enhanced Reliable Datagram Transport
Enforcing transaction order in peer-to-peer interactions
Network interface controller with direct connection to host memory
Self-Adjusting Cooling Module
Ip Route Caching with Two Search Stages on Prefix Length
Generating High-Speed Test Traffic in a Network Switch
Field Replaceable Modular Optical Interconnect Unit with Optical Module for Datacenter Switch System
Printed Circuit Board Assembly with a Photonic Integrated Circuit for an Electro-Optical Interface
Adaptive flow prioritization
Opto-Mechanical Coupler
Selective acknowledgment of RDMA packets
Laser Chip with Multiple Outputs on Common Side
Application:
15/197,066 →
Publication:
US 2018/0006433
Transducer Reliability Testing
Configuring Routing in Mesh Networks
Patent:
10,282,338 →
Application:
15/201,754 →
Access control in peer-to-peer transactions over a peripheral component bus
Scalable Deadlock-Free Deterministic Minimal-Path Routing for Dragonfly Networks
Application:
15/218,028 →
Publication:
US 2018/0026878
Backward Congestion Notification in Layer-3 Networks
High Performance, Scalable Multi Chip Interconnect
Patent:
10,367,741 →
Application:
15/244,171 →
Aggregation protocol
Silicon Photonics Connector
Efficient Matching of Tcam Rules Using Hash Tables in Ram
Edge Construction on Optical Devices
Patent:
9,835,801 →
Application:
15/273,615 →
Network Monitoring Using Selective Mirroring
Hardware-based congestion control for TCP traffic
Power Supply Voltage Monitoring and High-Resolution Adaptive Clock Stretching Circuit
Opto-Mechanical Coupler
Dynamic Optimization for IP Forwarding Performance
Cable Backplane
Simplified Packet Routing
Low-Complexity Measurement of Packet Traversal Time in Network Element
Fan-out joint for fiberoptic cables
Construction of Integrated Mode Transformers
Adaptive Routing Based on Flow-Control Credits
Method and Apparatus for Finding Logic Equivalence Between Register Transfer Level and Post Synthesis Nets
Automated control of descriptor type for packet transmission
Distribution of Messages to Queues in a Distributed Computing Environment
Multi-Stage Selective Mirroring
Hardware Device Safe Mode
Utilizing Management Network for Secured Configuration and Platform Management
Deadlock-Free Routing in Lossless Multidimensional Cartesian Topologies with Minimal Number of Virtual Buffers
Modular System for Datacenter Switch Systems and Routers
Adaptive Datacenter Connector
Method of Configuring an Optoelectronic System for Accommodating Different Fiber Optic Cable Lengths
Patent:
9,948,386 →
Application:
15/395,260 →
Fabric Wise Width Reduction
Application:
15/401,042 →
Publication:
US 2018/0199292
Integrated circuit inductor
Edge retainer for a printed circuit card
Patent:
816,473 →
Application:
29/573,801 →
Atomic access to object pool over RDMA transport network
Application:
62/304,348 →
In-node aggregation and disaggregation of MPI all2all and alltoallv collectives
Application:
62/304,355 →
Synchronized network stream switching by classifying flow attributes
Application:
62/336,763 →
Dynamically-tuned Interrupt Moderation
Application:
62/341,108 →
Estimated Counting of Distinct Flows
Application:
62/356,570 →
Integrating Silicon Photonics and Laser Dies Using Flip-Chip Technology
Application:
62/359,225 →
Credit Loop Deadlock Detection and Recovery in Arbitrary Topology Networks
Application:
62/362,072 →
Using Hardware Gather-Scatter Capabilities to Optimize MPI All-to-All
Application:
62/377,616 →
Algorithm for Coordinate Assignment in Pristine Partial Tori and Mesh Networks
Application:
62/426,240 →
Shortest-Path Routing Algorithm for Faulty Torus and Mesh Networks with Minimal Use of Virtual Lanes
Application:
62/426,241 →
Converting a Switch to a Packet Analyzer
Application:
62/426,644 →
Network-Based System and Method for Accelerating Deep Learning Classification
Application:
62/427,162 →
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 30, 2016
From: TYCO ELECTRONICS SERVICES GMBH
To: MELLANOX TECHNOLOGIES LTD.
Reel/Frame 039916/0074 →
Purchase Agreement
Feb 16, 2017
From: EZCHIP, INC.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0151 →
Merger
Feb 16, 2017
From: TILERA CORPORATION
To: EZCHIP SEMICONDUCTOR INC.
Reel/Frame 041735/0792 →
Dividend Declaration from Ezchip Semiconductor Inc. to the Stockholder of Record on 6/2/2015 (Ezchip Inc., a Delaware Corporation)
Feb 16, 2017
From: EZCHIP SEMICONDUCTOR INC.
To: EZCHIP, INC.
Reel/Frame 041736/0013 →
Assignment of Assignor's Interest
Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: EZCHIP TECHNOLOGIES, LTD.
Reel/Frame 041736/0253 →
Merger
Feb 16, 2017
From: EZCHIP TECHNOLOGIES LTD.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0321 →
Merger
Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041870/0455 →
Merger
Mar 13, 2017
From: EZCHIP TECHNOLOGIES LTD.; EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041550/0164 →
Merger
Mar 13, 2017
From: EZCHIP TECHNOLOGIES LTD.; EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041550/0181 →
Merger and Change of Name
Mar 13, 2017
From: EZCHIP TECHNOLOGIES LTD.; MELLANOX TECHNOLOGIES, LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041550/0105 →
Merger
Mar 13, 2017
From: EZCHIP TECHNOLOGIES LTD.; EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041550/0139 →
Release of Security Interest
Mar 15, 2017
From: PLENUS II LIMITED PARTNERSHIP
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 042009/0849 →
Release of Floating Charge Agreement
Mar 15, 2017
From: GOLDEN GATE BRIDGE FUND L.P. C/O PLENUS TECHNOLOGY
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 042009/0875 →
Release of Floating Charge Agreement
Mar 15, 2017
From: PLENUS TECHNOLOGY LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 042009/0880 →
Release of Security Interest in Patent Collateral at Reel/Frame No. 42962/0859
Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Reel/Frame 046551/0459 →