Configuring routing in mesh networks
View Patent ↗A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions and is configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first dimension ordering policy, and from the intermediate processor core to a destination processor core. The first dimension ordering policy specifies an ordering of the dimensions of the interconnection network when routing data through the interconnection network.
1. An apparatus, comprising:
a plurality of processor tiles, each processor tile comprising a processor core; and
an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions,
the interconnection network being configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first ordering policy of multiple ordering policies that specify an order of dimensions by which routing of data occurs over the interconnection network, with an order of dimensions that orders a first dimension before a second dimension indicating that data are to be routed along the first dimension followed by routing of data along the second dimension, and from the intermediate processor core to a destination processor core.
2. The apparatus of claim 1 in which the data is routed from the intermediate processor core to the destination processor core based on a second ordering policy of the multiple ordering policies.
3. The apparatus of claim 1 , comprising software to select one of the processor cores as the intermediate processor core, the software capable of identifying different intermediate processor cores for different applications.
4. The apparatus of claim 1 in which the intermediate processor core is selected to reduce or eliminate a skin effect and increase throughput of the interconnection network.
5. The apparatus of claim 1 in which the initial processor core generates headers of data packets such that the data packets can be routed through the intermediate processor core.
6. The apparatus of claim 1 in which the data is transmitted in a packet having a first header and a second header, the first header is used to route the packet from the initial processor core to the intermediate processor core, and the intermediate processor core is configured to remove the first header to expose the second header.
7. The apparatus of claim 1 in which the intermediate processor core is capable of updating the header of a data packet and generating the header for a remaining portion of the route to the destination processor core.
8. A processor, comprising:
a plurality of processor tiles, each tile comprising a processor core; and
an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions in which a first ordering of the dimensions is used for routing data from an input/output device to intermediate points, a second ordering of the dimensions is used for routing data from the intermediate points to the processor cores, a third ordering of the dimensions is used for routing data from the processor cores to the intermediate points, and a fourth ordering of the dimensions is used for routing data from the intermediate points to the input/output device, with at least two of the first, second, third, and fourth orderings of the dimensions being different, and with an ordering of dimensions that orders a first dimension before a second dimension indicating that data are to be routed along the first dimension followed by routing of data along the second dimension.
9. The processor of claim 8 , wherein the plurality of processor cores comprise a two-dimensional array of processor cores arranged in rows and columns of processor cores, a first row of processor cores connected to input/output ports that are coupled to corresponding input/output ports of a peripheral device, and in response to determining that there are more data being sent from the peripheral device to the processor cores, the plurality of processor cores route data using the first ordering of the dimensions specifying that data are to be routed along a column dimension followed by routing of the data along a row dimension.
10. The processor of claim 8 , wherein the plurality of processor cores comprise a two-dimensional array of processor cores arranged in rows and columns of processor cores, a first row of processor cores connected to input/output ports that are coupled to a peripheral device, and in response to determining that there are more data being sent from the processor cores to the peripheral device, the plurality of processor cores route data using the fourth ordering of the dimensions specifying that data are to be routed along a row dimension followed by routing of the data along a column dimension.
11. An apparatus, comprising:
a plurality of processor cores; and
an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions,
the interconnection network being configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first ordering policy of multiple ordering policies that specify an order of dimensions by which routing of data occurs over the interconnection network, with an order of dimensions that orders a first dimension before a second dimension indicating that data are to be routed along the first dimension followed by routing of data along the second dimension, and from the intermediate processor core to a destination processor core.
12. An apparatus, comprising:
a processor comprising
a plurality of processor tiles, each processor tile comprising a processor core, and
a multi-dimensional interconnection network to interconnect the processor cores and enable transfer of data among the processor cores; and
a memory controller having input/output ports that are coupled to corresponding input/output ports associated with some of the processor cores;
the processor configured to route read data packets from the memory controller to one or more intermediate processor cores based on a first ordering policy of multiple ordering policies that specify an order of dimensions by which routing of data occurs over the interconnection network, with an order of dimensions that orders a first dimension before a second dimension indicating that data are to be routed along the first dimension followed by routing of data along the second dimension, and from the one or more intermediate processor cores to destination processor cores based on a second ordering policy of the multiple ordering policies, the read data packets from the memory controller each having a header specifying an address of an intermediate processor core; and
the processor configured to route write data packets from one or more processor cores to one or more intermediate processor cores based on a third ordering policy of the multiple ordering policies, and from the one or more intermediate processor cores to the memory controller based on a fourth ordering policy of the multiple ordering policies, the write data packets from the processor cores each having a header specifying an address of an intermediate processor core.
13. A method, comprising:
receiving a data packet at a first processor core, the data packet having a destination that corresponds to a second processor core, the first and second processor cores being part of an array of processor tiles, each processor tile comprising a processor core, with an intermediate processor core capable of determining a next intermediate processor core based on an ordering policy of multiple ordering policies that specify an order of dimensions by which routing of data occurs over the interconnection network, with an order of dimensions that orders a first dimension before a second dimension indicating that data are to be routed along the first dimension followed by routing of data along the second dimension;
modifying a header of the data packet to specify an intermediate processor core;
routing the data packet from the first processor core to the intermediate processor core through an interconnection network that interconnects the array of processor tiles; and
routing the data packet from the intermediate processor core to the second processor core.
14. The method of claim 13 , comprising selecting the intermediate processor core to reduce or eliminate a skin effect.
15. The method of claim 13 in which intermediate processor cores are determined by a mapping table which can be programmed by software.